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ISL6173_06 Datasheet(数据表) 14 Page - Intersil Corporation

部件型号  ISL6173
说明  Dual Low Voltage Hot Swap Controller
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制造商  INTERSIL [Intersil Corporation]
网页  http://www.intersil.com/cda/home
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ISL6173 Datasheet(HTML) 14 Page - Intersil Corporation

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14
FN9186.3
January 3, 2006
Soft-Start Capacitor Selection (CSS)
The rate of change of voltage (dv/dt) on this capacitor, which
is determined by the internal 10µA current source, is the
same as that on the output load capacitance. Hence, the
value of this capacitor directly controls the inrush current
amplitude during hot swap operation.
CSS = CO*(10µA/IINRUSH)
Where,
CO = Load Capacitance
IINRUSH = Desired Inrush Current
IINRUSH is the sum of the dc steady-state load current and
the load capacitance charging current. If the dc steady-state
load remains disabled until after the soft-start period expires
(PGx could be used as a load enable signal, for example),
then only the capacitor charging current should be used as
IINRUSH. The Css value should always be more than (1/2.4)
of that of Ciss of the MOSFET to ensure proper soft-start
operation. This is because the Ciss is charged from 24µA
current source whereas the Css gets charged from a 10µA
current source (please refer to Figure 12). In order to make
sure both Vss and Vo track during the soft-start, this
condition is necessary.
ISL6173 Evaluation Platform
The ISL6173EVAL1 is the primary evaluation board for this
IC. The board is a standalone evaluation platform and it only
needs input bias and test voltages. The schematic for this
board is shown in Figures 20 and 21. The component
placement diagram is shown in Figure 22.
The evaluation board has been designed with a typical
application and accessibility to all the features in mind to
enable a user to understand and verify these features of the
IC. The circuit is designed for 2A for each input rail but it can
easily be scaled up or down by adjusting some component
values. LED indicators are provided to indicate Fault and
Power Good status. Switches are there to perform Enable
function for each channel, to select auto-retry or latchoff
mode and to check WOC and CR modes.
There are two input voltages, one for each channel plus
there is “+5V” input. The latter is to test the pull-up capability
of FLT and PG outputs to +5V and also to power the LEDs
and the dynamic load circuitry. ISL6173 does not require 5V.
Pins SS1 and SS2 of the IC are available on header J2 as
test points so that they can be tied together to achieve
tracking between Vo1 and Vo2. Both the Enable (EN)
switches (SW1 and SW2) must be turned ON to check this
function.
Each channel is preloaded with capacitive load. Extra load
can be externally applied as required.
The outputs are brought out to banana sockets to allow
external loading if desired.
J1 and J3 are wire jumpers. A user can replace them with
wire loops to attach a scope current probe. However, doing
so may reduce the di/dt enough to prevent WOC comparator
from tripping. The internal current regulation amplifier is fast
enough to respond to very fast di/dt. Hence, it is advisable to
use the on board dynamic load circuitry, as will be described,
if a user wants to check the WOC performance.
The dynamic load circuitry, shown in Figure 21, is included
on the board on both channels to ensure minimum
inductance in the current flow path. Two sets of load are
available per output:
1) CR Load: This load is set at 1
Ω (approximately 3.3A for
3.3V output), which is higher than the 2.2A of CR limit but
less than WOC limit (6.6A) set on the board.
2) WOC Load: This load is set at 340m
Ω, which is roughly
10A for 3.3V supply. This is higher than 6.6A WOC limit set
on the board.
A function/pulse generator is required to activate the
dynamic load circuitry. The function/pulse generator should
have adjustable pulse-width (3ms), single pulse (manual
trigger) and 5V pulse amplitude capability. Agilent model
No: 33220A or equivalent is a good choice. The function
generator needs to be connected through a co-ax cable to
J11 or J12 for channel 1 or channel 2 respectively. WOC or
CR load can be activated by turning SW4 or SW5 (channel
1) and SW6 or SW7 (channel 2) ON followed by applying the
pulse generator to turn on an appropriate load.
The load circuit consists of a MOSFET driver (EL7202),
MOSFET (IRF7821) and surface mount load resistors. The
MOSFET drivers, U2 and U3, respond to a pulse from the
generator to turn on the MOSFET for the duration of the
pulse, which should be set less than the timeout period
described in “Time-out Capacitor Selection”. On this board
the timeout capacitor value is 0.15µF, which corresponds to
a timeout period of 17.67ms.
One way to tell if the WOC mode is active would be by
looking at the Gate waveform of the control MOSFET (M1 or
M2). The WOC comparator when tripped, pulls down the
Gate hard. The following waveform shows WOC operation:
ISL6173




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