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ISL6173_06 Datasheet(数据表) 3 Page - Intersil Corporation |
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ISL6173 Datasheet(HTML) 3 Page - Intersil Corporation |
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3 page 
3 FN9186.3 January 3, 2006 Pinout 28 LEAD QFN TOP VIEW 1 2 3 4 5 6 7 21 20 19 18 17 16 15 28 27 26 25 24 23 22 8 9 10 11 12 13 14 SNS2 VO2 SS2 GT2 FLT2 PG2 CT2 SNS1 VO1 SS1 GT1 FLT1 PG1 CT1 Pin Descriptions PIN NAME FUNCTION DESCRIPTION 1 SNS1 Current Sense Input This pin is connected to the current sense resistor and control MOSFET Drain node. It provides current sense signal to the internal comparator and amplifier in conjunction with VS1 pin. 2 VO1 Output Voltage 1 This pin is connected to the control MOSFET switch source, which connects to a load. Internally, this voltage is used for SS control. 3 SS1 Soft-Start Duration Set Input A capacitor from this pin to ground sets the output soft-start ramp slope. This capacitor is charged by the internal 10µA current source setting the soft-start ramp. The output voltage ramp tracks the SS ramp by controlled enhancement of FET gate. Once ramp-up is completed, the capacitor continues to charge to the CPVDD voltage rail. If common capacitor is used (by tying SS1, SS2 together and the capacitor to GND from the connection) then both the outputs track each other as they ramp up. 4 GT1 Gate Drive Output Direct connection to the gate of the external N-Channel MOSFET. At turn-on the Gate will charge to 4 X Vbias or 10V(max) from the 24µA source. 5FLT1 Fault Output This is an open drain output. It asserts (pulls low) once the current regulation duration (determined by the CTx timeout cap) has expired. This output is valid for Vbias>1V. 6PG1 Power Good Output This is an active low, open drain output. When asserted (logic zero), it indicates that the voltage on UV1 pin is more than 643mV (633mV + 10mV hysteresis). This output is valid at VBIAS >1V. 7 CT1 Timer Capacitor A capacitor from this pin to ground controls the current regulation duration from the onset of current regulation to channel shutdown (current limit time-out). Once the voltage on CTx cap reaches VCT_Vth the GATE output is pulled down and the FLT is asserted. The duration of current limit time-out = (CTIM*1.178)/10µA When the OC comparator trips AND the RTR/LTCH pin is pulled low, the IC’s faulty channel remains shut down for 64 cycles (each cycle length is equal to the current limit time-out duration). 8RTR/ LTCH Retry Or Latch Input This input dictates the IC behavior (for either channel) under OC condition. If it is pulled high (or left floating), the IC will shut down upon OC time-out. If it is pulled low, the IC will go into retry mode after an interval determined by the capacitor on CTx pin. The faulting channel will remain shut down for 64 cycles and will try to come out of it on the 65th cycle. Each cycle length is determined by the formula shown in CT pin description. 9 GND Chip Gnd This pin is also internally shorted to the metal tab at the bottom of the IC. 10 PGND Charge pump ground. Both GND and PGND must be tied together externally. ISL6173 |
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