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FIN24AC 数据表(PDF) 3 Page - Fairchild Semiconductor |
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FIN24AC 数据表(HTML) 3 Page - Fairchild Semiconductor |
3 / 25 page © 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN24AC Rev. 1.0.3 3 Terminal Description Note: 1. The DSO/DSI serial port terminals have been arranged such that when one device is rotated 180° to the other device, the serial connections properly align without the need for any traces or cable signals to cross. Other layout orientations may require that traces or cables cross. Terminal Name I/O Type Number of Terminals Description of Signals DP[1:20] I/O 20 LVCMOS Parallel I/O, direction controlled by DIRI pin DP[21:22] I 2 LVCMOS Parallel Unidirectional Inputs DP[23:24] O 2 LVCMOS Unidirectional Parallel Outputs CKREF IN 1 LVCMOS Clock Input and PLL Reference STROBE IN 1 LVCMOS Strobe Signal for Latching Data into the Serializer CKP OUT 1 LVCMOS Word Clock Output DSO+ / DSI– DSO– / DSI+ DIFF-I/O 2 CTL Differential Serial I/O Data Signals(1) DSO: Refers to output signal pair DSI: Refers to input signal pair DSO(I)+: Positive signal of DSO(I) pair DSO(I)–: Negative signal of DSO(I) pair CKSI+, CKSI– DIFF-IN 2 CTL Differential Deserializer Input Bit Clock CKSI: Refers to signal pair CKSI+: Positive signal of CKSI pair CKSI–: Negative signal of CKSI pair CKSO+, CKSO– DIFF-OUT 2 CTL Differential Serializer Output Bit Clock CKSO: Refers to signal pair CKSO+: Positive signal of CKSO pair CKSO–: Negative signal of CKSO pair S1 IN 1 LVCMOS Mode Selection terminals used to select Frequency Range for the RefClock, CKREF S2 IN 1 DIRI IN 1 LVCMOS Control Input Used to control direction of Data Flow: DIRI = “1” Serializer, DIRI = “0” Deserializer DIRO OUT 1 LVCMOS Control Output Inversion of DIRI VDDP Supply 1 Power Supply for Parallel I/O and Translation Circuitry VDDS Supply 1 Power Supply for Core and Serial I/O VDDA Supply 1 Power Supply for Analog PLL Circuitry GND Supply 0 Use Bottom Ground Plane for Ground Signals |
类似零件编号 - FIN24AC |
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类似说明 - FIN24AC |
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