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FIN12ACGFX 数据表(PDF) 5 Page - Fairchild Semiconductor |
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FIN12ACGFX 数据表(HTML) 5 Page - Fairchild Semiconductor |
5 / 24 page © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN12AC Rev. 1.1.0 5 Serializer Operation Mode The serializer configurations are described in the following sections. The basic serialization circuitry works similarly in these modes, but the actual data and clock streams differ, dependent on whether CKREF is the same as the STROBE signal. When it is stated that CKREF = STROBE, the CKREF and STROBE signals have an identical frequency of operation, but may or may not be phase aligned. When it is stated that CKREF does not equal STROBE, each signal is distinct and CKREF must be running at a frequency high enough to avoid any loss of data condition. CKREF must never be a lower frequency than STROBE. The PLL must receive a stable CKREF signal to achieve lock prior to any valid data being sent. During the PLL phase, STROBE should not be connected to the CKREF signal. Once the PLL is stable and locked, the device can begin to capture and serialize data. Data is captured on the rising edge of the STROBE signal and serialized. The serialized data stream is synchronized and sent source synchronously with a bit clock with an embedded word boundary. When operating in this mode, the internal deserializer circuitry is disabled, including the DS input buffer. The CKSI serial inputs remain active to allow the pass through of the CKSI signal to the CKP output. For more on this mode, please see the section on Passing a Word Clock. If this mode is not needed, the CKSI inputs can either be driven to valid levels or left to float. For lowest power operation, let the CKSI inputs float. Figure 3. Serializer Timing Diagram (CKREF = STROBE) If the same signal is not used for CKREF and STROBE, the CKREF signal must be run at a higher frequency than the STROBE rate to serialize the data correctly. The actual serial transfer rate remains at 14 times the CKREF frequency. A data value of zero is sent when no valid data is present in the serial bit stream. The operation of the serializer otherwise remains the same. The exact frequency that the reference clock needs is dependent upon the stabil- ity of the CKREF and STROBE signal. If the source of the CKREF signal imple- ments spread spectrum technology, the minimum frequency of this spread spectrum clock should be used in calculating the ratio of STROBE frequency to the CKREF frequency. Similarly if the STROBE signal has significant cycle-to- cycle variation, the maximum cycle-to-cycle time needs to be factored into the selection of the CKREF frequency. Figure 4. Serializer Timing Diagram (CKREF does not = STROBE) WORD n-1 WORD n-2 WORD n-1 WORD n DP[1:12] CKREF/STROBE DSO CKSO b12 b13 b14 b1 b2 b3 b4 b5 b6 b7 b13 b14 b1 b2 b3 b8 b9 b10 b11 b12 WORD n+1 WORD n No Data WORD n-1 WORD n DP[1:12] STROBE DSO WORD n–1 WORD n WORD n+1 No Data CKREF CKSO b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b1 b2 b3 Serializer Operation: (Figure 3) Modes 1, 2, 3 DIRI = 1, CKREF = STROBE Serializer Operation: (Figure 4) DIRI = 1, CKREF does not = STROBE |
类似零件编号 - FIN12ACGFX |
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类似说明 - FIN12ACGFX |
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