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P87C552 数据表(PDF) 6 Page - NXP Semiconductors |
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P87C552 数据表(HTML) 6 Page - NXP Semiconductors |
6 / 74 page Philips Semiconductors Preliminary specification P87C552 80C51 8-bit microcontroller 8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, low voltage (2.7V–5.5V), low power 1999 Mar 30 6 PIN DESCRIPTION (Continued) PIN NO. MNEMONIC PLCC QFP TYPE NAME AND FUNCTION P4.0-P4.7 7-14 80, 1-2 4-8 I/O Port 4: 8-bit programmable I/O port. Alternate functions include: 7-12 80, 1-2 4-6 O CMSR0-CMSR5 (P4.0-P4.5): Timer T2 compare and set/reset outputs on a match with timer T2. 13, 14 7, 8 O CMT0, CMT1 (P4.6, P4.7): Timer T2 compare and toggle outputs on a match with timer T2. Port 4 has four modes selected on a per bit basis by writing to the P4M1 and P4M2 registers as follows: P4M1.x P4M2.x Mode Description 0 0 Pseudo-bidirectional (standard c51 configuration; default) 0 1 Push-Pull 1 0 High impedance 1 1 Open drain P5.0-P5.7 68-62, 1 71-64 I Port 5: 8-bit input port. 1 ADC0-ADC7 (P5.0-P5.7): Alternate function: Eight input channels to the ADC. RST 15 9 I/O Reset: Input to reset the 87C552. It also provides a reset pulse as output when timer T3 overflows. XTAL1 35 32 I Crystal Input 1: Input to the inverting amplifier that forms the oscillator, and input to the internal clock generator. Receives the external clock signal when an external oscillator is used. XTAL2 34 31 O Crystal Input 2: Output of the inverting amplifier that forms the oscillator. Left open-circuit when an external clock is used. VSS 36, 37 34-36 I Digital ground. PSEN 47 48 O Program Store Enable: Active-low read strobe to external program memory. ALE/PROG 48 49 O Address Latch Enable: Latches the low byte of the address during accesses to external memory. It is activated every six oscillator periods. During an external data memory access, one ALE pulse is skipped. ALE can drive up to eight LS TTL inputs and handles CMOS inputs without an external pull-up. This pin is also the program pulse input (PROG) during EPROM programming. EA/VPP 49 50 I External Access: When EA is held at TTL level high, the CPU executes out of the internal program ROM provided the program counter is less than 8,192. When EA is held at TTL low level, the CPU executes out of external program memory. EA is not allowed to float. This pin also receives the 12.75V programming supply voltage (VPP) during EPROM programming. AVREF– 58 59 I Analog to Digital Conversion Reference Resistor: Low-end. AVREF+ 59 60 I Analog to Digital Conversion Reference Resistor: High-end. AVSS 60 61 I Analog Ground AVDD 61 63 I Analog Power Supply NOTE: 1. To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher or lower than VDD + 0.5V or VSS – 0.5V, respectively. |
类似零件编号 - P87C552 |
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类似说明 - P87C552 |
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