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X1288V14IZ-2.7 数据表(PDF) 6 Page - Intersil Corporation |
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X1288V14IZ-2.7 数据表(HTML) 6 Page - Intersil Corporation |
6 / 27 page 6 FN8102.3 April 14, 2006 AC Specifications (TA = -40°C to +85°C, VCC = +2.7V to +5.5V, unless otherwise specified.) Notes: (1) This parameter is not 100% tested. (2) Cb = total capacitance of one bus line in pF. TIMING DIAGRAMS Bus Timing Write Cycle Timing Symbol Parameter Min. Max. Units fSCL SCL Clock Frequency 400 kHz tIN Pulse width Suppression Time at inputs 50(1) ns tAA SCL LOW to SDA Data Out Valid 0.9 µs tBUF Time the bus must be free before a new transmission can start 1.3 µs tLOW Clock LOW Time 1.3 µs tHIGH Clock HIGH Time 0.6 µs tSU:STA Start Condition Setup Time 0.6 µs tHD:STA Start Condition Hold Time 0.6 µs tSU:DAT Data In Setup Time 100 ns tHD:DAT Data In Hold Time 0 µs tSU:STO Stop Condition Setup Time 0.6 µs tDH Data Output Hold Time 50 ns tR SDA and SCL Rise Time 20 +.1Cb(1)(2) 300 ns tF SDA and SCL Fall Time 20 +.1Cb(1)(2) 300 ns Cb Capacitive load for each bus line 400 pF tSU:STO tDH tHIGH tSU:STA tHD:STA tHD:DAT tSU:DAT SCL SDA IN SDA OUT tF tLOW tBUF tAA tR SCL SDA tWC 8th Bit of Last Byte ACK Stop Condition Start Condition X1288 |
类似零件编号 - X1288V14IZ-2.7 |
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类似说明 - X1288V14IZ-2.7 |
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