7

FN7452.4

January 5, 2007

FIGURE 21. PACKAGE POWER DISSIPATION vs AMBIENT

TEMPERATURE

FIGURE 22. PACKAGE POWER DISSIPATION vs AMBIENT

TEMPERATURE

Pin Descriptions

PIN NUMBER

PIN NAME

EQUIVALENT

CIRCUIT

DESCRIPTION

1

IN0

Circuit 1

Input for channel 0

2, 6, 9

NIC

Not Internally Connected; it is recommended this pin be tied to ground to

minimize crosstalk.

3

IN1

Circuit 1

Input for channel 1

4

GND

Circuit 4

Ground pin

5

IN2

Circuit 1

Input for channel 2

7

IN3

Circuit 1

Input for channel 3

8

V-

Circuit 4

Negative power supply

10

OUT

Circuit 3

Output

11

HIZ

Circuit 2

Output disable (active high); there are internal pull-down resistors, so the

device will be active with no connection; "HI" puts the output in high

impedance state.

12

S1

Circuit 2

Channel selection pin MSB (binary logic code)

13

S0

Circuit 2

Channel selection pin LSB (binary logic code)

14

V+

Circuit 4

Positive power supply

1.136W

θ

88

°C

/W

SO

14

1.4

1.2

1

0.8

0.6

0.2

0

0

25

50

75

100

150

AMBIENT TEMPERATURE (°C)

125

85

JEDEC JESD51-7 HIGH EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD

0.4

833mW

θ

12

0°C

/W

SO

14

1

0.9

0.8

0.6

0.4

0.1

0

025

50

75

100

150

AMBIENT TEMPERATURE (°C)

125

85

JEDEC JESD51-3 LOW EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD

0.2

0.7

0.3

0.5

IN

V+

V-

CIRCUIT 1.

LOGIC PIN

V+

V-

GND.

33k

21k

+

-

1.2V

CIRCUIT 2.

V+

V-

OUT

CIRCUIT 3.

V-

V+

CAPACITIVELY

COUPLED

ESD CLAMP

GND

CIRCUIT 4.

ISL59442