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AM29LV010B-55JE 数据表(PDF) 11 Page - Advanced Micro Devices

部件名 AM29LV010B-55JE
功能描述  1 Megabit (128 K x 8-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory
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制造商  AMD [Advanced Micro Devices]
网页  http://www.amd.com
标志 AMD - Advanced Micro Devices

AM29LV010B-55JE 数据表(HTML) 11 Page - Advanced Micro Devices

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October 11, 2006 22140D6
Am29LV010B
11
D A TA SH EE T
system can then read autoselect codes from the
internal register (which is separate from the memory
array) on DQ7–DQ0. Standard read cycle timings apply
in this mode. Refer to the Autoselect Mode and Autose-
lect Command Seque nce sect ions fo r mo re
information.
ICC2 in the DC Characteristics table represents the
active current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and ICC
read specifications apply. Refer to “Write Operation
Status” for more information, and to “AC Characteris-
tics” for timing diagrams.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
The device enters the CMOS standby mode when the
CE# pin is held at VCC ± 0.3 V. (Note that this is a more
restricted voltage range than VIH.) If CE# is held at VIH,
but not within VCC ± 0.3 V, the device will be in the
standby mode, but the standby current will be greater.
The device requires standard access time (tCE) for read
access when the device is in either of these standby
modes, before it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
ICC3 in the DC Characteristics table represents the
standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically enables
this mode when addresses remain stable for tACC + 30
ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard address
access timings provide new data when addresses are
changed. While in sleep mode, output data is latched
and always available to the system. ICC4 in the DC
Characteristics table represents the automatic sleep
mode current specification.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high imped-
ance state.
Table 2.
Am29LV010B Uniform Sector Address Table
Sector
A16
A15
A14
Address Range
SA0
0
0
0
00000h-03FFFh
SA1
0
0
1
04000h-07FFFh
SA2
0
1
0
08000h-0BFFFh
SA3
0
1
1
0C000h-0FFFFh
SA4
1
0
0
10000h-13FFFh
SA5
1
0
1
14000h-17FFFh
SA6
1
1
0
18000h-1BFFFh
SA7
1
1
1
1C000h-1FFFFh


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