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AM29F080B-70SD 数据表(PDF) 10 Page - Advanced Micro Devices |
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AM29F080B-70SD 数据表(HTML) 10 Page - Advanced Micro Devices |
10 / 39 page 8 Am29F080B 21503G5 November 1, 2006 D A TA SH EE T DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register it- self does not occupy any addressable memory loca- tion. The register is composed of latches that store the commands, along with the address and data informa- tion needed to execute the command. The contents of the register serve as inputs to the internal state ma- chine. The state machine outputs dictate the function of the device. The appropriate device bus operations table lists the inputs and control levels required, and the resulting output. The following subsections describe each of these operations in further detail. Table 1. Am29F080B Device Bus Operations Legend: L = Logic Low = VIL, H = Logic High = VIH, DOUT = Data Out, DIN = Data In, AIN = Address In, X = Don’t Care. See DC Charac- teristics for voltage levels. Note: See the sections on Sector Group Protection and Temporary Sector Unprotect for more information. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should re- main at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the mem- ory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that as- sert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See “Reading Array Data” for more information. Refer to the AC Read Operations table for timing specifica- tions and to the Read Operations Timings diagram for the timing waveforms. ICC1 in the DC Characteristics table represents the active current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. An erase operation can erase one sector, multiple sec- tors, or the entire device. The Sector Address Tables in- dicate the address space that each sector occupies. A “sector address” consists of the address bits required to uniquely select a sector. See the Command Defini- tions section for details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command se- quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autoselect Command Sequence sections for more information. ICC2 in the DC Characteristics table represents the ac- tive current specification for the write mode. The “AC Characteristics” section contains timing specification tables and timing diagrams for write operations. Program and Erase Operation Status During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and ICC read specifications apply. Refer to “Write Operation Operation CE# OE# WE# RESET# A0–A19 DQ0 –DQ7 Read L L X H AIN DOUT Write L H L H AIN DIN TTL Standby H X X H X HIGH Z CMOS Standby VCC ± 0.3 V X X VCC ± 0.3 V X HIGH Z Output Disable L H H H X HIGH Z Hardware Reset X X X VIL XHIGH Z Temporary Sector Group Unprotect (See Note) X X X VID AIN X |
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