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IRFZ44NS 数据表(PDF) 1 Page - NXP Semiconductors |
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IRFZ44NS 数据表(HTML) 1 Page - NXP Semiconductors |
1 / 8 page Philips Semiconductors Product specification N-channel enhancement mode IRFZ44NS TrenchMOS TM transistor GENERAL DESCRIPTION QUICK REFERENCE DATA N-channel enhancement mode SYMBOL PARAMETER MAX. UNIT standard level field-effect power transistor in a surface mounting V DS Drain-source voltage 55 V plastic envelope using ’trench’I D Drain current (DC) 49 A technology. The device features very P tot Total power dissipation 110 W low on-state resistance and has T j Junction temperature 175 ˚C integral zener diodes giving ESD R DS(ON) Drain-source on-state 22 m Ω protection up to 2kV. It is intended for resistance V GS = 10 V use in switched mode power supplies and general purpose switching applications. PINNING - SOT404 (D 2PAK) PIN CONFIGURATION SYMBOL PIN DESCRIPTION 1 gate 2 drain 3 source mb drain LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT V DS Drain-source voltage - - 55 V V DGR Drain-gate voltage R GS = 20 kΩ -55 V ±V GS Gate-source voltage - - 20 V I D Drain current (DC) T mb = 25 ˚C - 49 A I D Drain current (DC) T mb = 100 ˚C - 35 A I DM Drain current (pulse peak value) T mb = 25 ˚C - 160 A P tot Total power dissipation T mb = 25 ˚C - 110 W T stg, Tj Storage & operating temperature - - 55 175 ˚C ESD LIMITING VALUE SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT V C Electrostatic discharge capacitor Human body model - 2 kV voltage, all pins (100 pF, 1.5 k Ω) THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT R th j-mb Thermal resistance junction to - - 1.4 K/W mounting base R th j-a Thermal resistance junction to Minimum footprint, FR4 50 - K/W ambient board d g s 13 mb 2 February 1999 1 Rev 1.000 |
类似零件编号 - IRFZ44NS |
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类似说明 - IRFZ44NS |
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