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CA3310A 数据表(PDF) 11 Page - Intersil Corporation |
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CA3310A 数据表(HTML) 11 Page - Intersil Corporation |
11 / 16 page 11 period 1, and is not reapplied during that period, the clock will shut off after entering period 2. The input will continue to track the DRDY output will remain high during this time. A low signal applied to STRT (at least tW STRT wide) can now initiate a new conversion. The STRT signal (after a delay of tD3 DRDY) will cause the DRDY flag to drop, and (after a delay of tD CLK) cause the clock to restart. Depending on how long the clock was shut off, the low portion of clock period 2 may be longer than during the remaining cycles. The input will continue to track until the end of period 3, the same as when free-running. Figure 4 illustrates the same operation as above, but with an external clock. If STRT is removed (at least tR STRT) before clock period 1, and not reapplied during that period, the clock will continue to cycle in period 2. A low signal applied to STRT will drop the DRDY flag as before, and with the first positive-going clock edge that meets the tSU STRT set-up time, the converter will continue with clock period 3. The DRDY flag output, as described previously, goes active at the start of period 1, and drops at the start of period 2 or upon a new STRT command, whichever is later. It may also be controlled with the DRST (Data Ready Reset) input. Figure 5 depicts this operation. DRST must be removed (at least tR DRST) before the start of period 1 to allow DRDY to go high. A low level on DRST (at least tW DRST wide) will (after a delay of tD4 DRDY) drop DRDY. Analog Input The analog input pin is a predominantly capacitive load that changes between the track and hold periods of a conversion cycle. During hold, clock period 4 through 13, the input loading is leakage and stray capacitance, typically less than 0.1 µA and 20pF. At the start of input tracking, clock period 1, some charge is dumped back to the input pin. The input source must have low enough impedance to dissipate the charge by the end of the tracking period. The amount of charge is dependent on supply and input voltages. Figure 8 shows typical peak input currents for various supply and input voltages, while Figure 9 shows typical average input currents. The average current is also proportional to clock frequency, and should be scaled accordingly. During tracking, the input appears as approximately a 300pF capacitor in series with 330 Ω, for a 100ns time constant. A full-scale input swing would settle to 1/2 LSB ( 1/ 2048) in 7RC time constants. Doing continuous conversions with a 1MHz clock provides 3 µs of tracking time, so up to 1kΩ of external source impedance (400ns time constant) would allow proper settling of a step input. If the clock was slower, or the converter was not restarted immediately (causing a longer sample lime), a higher source impedance could be used. The CA3310s low-input time constant also allows good tracking of dynamic input waveforms. The sampling rate with a 1MHz clock is approximately 80kHz. A Nyquist rate (fSAMPLE/2) input sine wave of 40kHz would have negligible attenuation and a phase lag of only 1.5 degrees. Accuracy Specifications The CA3310 accepts an analog input between the values of VREF- and VREF+, and quantizes it into one of 2 10 or 1024 output codes. Each code should exist as the input is varied through a range of 1/1024 x (VREF+ - VREF-), referred to as 1 LSB of input voltage. A differential Iinearity error, illustrated in Figure 17, occurs if an output code occurs over other than the ideal (1 LSB) input range. Note that as long as the error does not reach -1 LSB, the converter will not miss any codes. The CA3310 output should change from a code of 00016 to 00116 at an input voltage of (VREF- +1 LSB). It should also change from a code of 3FE16 to 3FF16 at an input of (VREF + -1 LSB). Any differences between the actual and expected input voltages that cause these transitions are the offset and gain errors, respectively. Figure 18 illustrates these errors. As the input voltage is increased linearly from the point that causes the 00016 to 00116 transition to the point that causes the 3FE16 to 3FF16 transition, the output code should also increase linearly. Any deviation from this input-to-output correspondence is integral linearity error, illustrated in Figure 19. Note that the integral linearity is referenced to a straight line drawn through the actual end points, not the ideal end points. For absolute accuracy to be equal to the integral linearity, the gain and offset would have to be adjusted to ideal. Offset and Gain Adjustments The VREF+ and VREF- pins, references for the two ends of the analog input range, are the only means of doing offset or UNIFORM TRANSFER CURVE A B C ACTUAL TRANSFER CURVE OUTPUT CODE A = IDEAL 1 LSB STEP B-A = + DIFFERENTIAL LINEARITY ERROR A-C = - DIFFERENTIAL LINEARITY ERROR INPUT VOLTAGE FIGURE 17. DIFFERENTIAL LINEARITY ERROR CA3310, CA3310A |
类似零件编号 - CA3310A |
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类似说明 - CA3310A |
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