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CD4070BE 数据表(PDF) 1 Page - Harris Corporation

部件名 CD4070BE
功能描述  CMOS Quad Exclusive-OR and Exclusive-NOR Gate
Download  7 Pages
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制造商  HARRIS [Harris Corporation]
网页  http://www.harris.com
标志 HARRIS - Harris Corporation

CD4070BE 数据表(HTML) 1 Page - Harris Corporation

  CD4070BE Datasheet HTML 1Page - Harris Corporation CD4070BE Datasheet HTML 2Page - Harris Corporation CD4070BE Datasheet HTML 3Page - Harris Corporation CD4070BE Datasheet HTML 4Page - Harris Corporation CD4070BE Datasheet HTML 5Page - Harris Corporation CD4070BE Datasheet HTML 6Page - Harris Corporation CD4070BE Datasheet HTML 7Page - Harris Corporation  
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1
Semiconductor
Features
• High-Voltage Types (20V Rating)
• CD4070B - Quad Exclusive-OR Gate
• CD4077B - Quad Exclusive-NOR Gate
• Medium Speed Operation
-tPHL, tPLH = 65ns (Typ) at VDD = 10V, CL = 50pF
• 100% Tested for Quiescent Current at 20V
• Standardized Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1
µA at 18V Over Full
Package Temperature Range
- 100nA at 18V and 25oC
• Noise Margin (Over Full Package Temperature Range)
- 1V at VDD = 5V, 2V at VDD = 10V, 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Standard No. 13B,
“Standard Specifications for Description of ‘B’ Series
CMOS Devices
Applications
• Logical Comparators
• Adders/Subtractors
• Parity Generators and Checkers
Description
The Harris CD4070B contains four independent Exclusive-
OR gates. The Harris CD4077B contains four independent
Exclusive-NOR gates.
The CD4070B and CD4077B provide the system designer
with a means for direct implementation of the Exclusive-OR
and Exclusive-NOR functions, respectively.
Pinouts
Ordering Information
PART NUMBER
TEMP.
RANGE (oC)
PACKAGE
PKG.
NO.
CD4070BE
-55 to 125
14 Ld PDIP
E14.3
CD4077BE
-55 to 125
14 Ld PDIP
E14.3
CD4070BF
-55 to 125
14 Ld CERDIP
F14.3
CD4077BF
-55 to 125
14 Ld CERDIP
F14.3
CD4070BM
-55 to 125
14 Ld SOIC
M14.15
CD4077BM
-55 to 125
14 Ld SOIC
M14.15
CD4070B
(PDIP, CERDIP, SOIC)
TOP VIEW
CD4077B
(PDIP, CERDIP, SOIC)
TOP VIEW
A
B
J = A
B
K = C
D
C
D
VSS
VDD
H
G
M = G
H
L = E
F
F
E
1
2
3
4
5
6
7
14
13
12
11
10
9
8
A
B
J = A
B
K = C
D
C
D
VSS
VDD
H
G
M = G
H
L = E
F
F
E
1
2
3
4
5
6
7
14
13
12
11
10
9
8
June 1998
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1998
CD4070B,
CD4077B
CMOS Quad Exclusive-OR
and Exclusive-NOR Gate
File Number
910.1


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