3-3

Input Impedance Components

Resistance (See Figure 14)

-

1600

-

-

170

-

10

20

-

k

Ω

Capacitance at 1MHz

-

2.7

-

-

2.7

-

-

2.7

-

pF

Output Impedance Components

Resistance (See Figure 15)

-

200

-

-

20

-

-

2

-

M

Ω

Capacitance at 1MHz

-

4.5

-

-

4.5

-

-

4.5

-

pF

Voltage (See Figure 16)

Temperature

6.2

6.7

7.9

V

Impedance

-

200

300

Ω

NOTES:

3. Conditions for Input Offset Voltage Sensitivity:

a. Bias current derived from the regulator with an appropriate resistor connected from Terminal 1 to the bias terminal on the amplifier

under test V+ is reduced to +13V for V+ sensitivity and V- is reduced to -13V for V- sensitivity.

b. V+ Sensitivity in

,

V- Sensitivity in

.

Electrical Specifications

(Continued)

PARAMETER

SYMBOL

AMPLIFIER BIAS CURRENT

UNITS

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

µVV

⁄

V

O ffset

V

O ffset

for +13V and -15V Supplies

–

1V

------------------------------------------------------------------------------------------------------------------------------

=

µVV

⁄

V

O ffset

V

O ffset

for -13V and +15V Supplies

–

1V

------------------------------------------------------------------------------------------------------------------------------

=

Schematic Diagram

BIAS REGULATOR AND ONE OPERATIONAL TRANSCONDUCTANCE AMPLIFIER

NOTES:

5. Inverting Input of Amplifiers 1, 2 and 3 is on Terminals 13, 12 and 4, respectively.

6. Non-inverting Input of Amplifiers 1, 2 and 3 is Terminals 14, 11 and 5, respectively.

7. Amplifier Bias Current of Amplifiers 1, 2 and 3 is on Terminals 15, 10 and 6, respectively.

8. Output of Amplifiers 1, 2 and 3 is on Terminals 16, 9 and 7, respectively.

2

1

INVERTING INPUT

-

+

(NOTE 5)

NON-INVERTING INPUT

(NOTE 6)

ZENER BIAS REGULATOR

AMPLIFIER BIAS INPUT

(NOTE 7)

3

8

OUTPUT (NOTE 8)

V+

V-

CA3060