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SY89847U Datasheet(数据表) 3 Page - Micrel Semiconductor

部件型号  SY89847U
说明  1.5GHz Precision, LVDS 1:5 Fanout with 2:1 MUX and Fail Safe Input with Internal Termination
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制造商  MICREL [Micrel Semiconductor]
网页  http://www.micrel.com
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SY89847U Datasheet(HTML) 3 Page - Micrel Semiconductor

 
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Micrel, Inc.
SY89847U
March 2007
M9999-031307-A
hbwhelp@micrel.com or (408) 955-1690
3
Pin Description
Pin Number
Pin Name
Pin Function
1, 8
VT0, VT1
Input Termination Center-Tap: Each side of a differential input pair terminates to
the VT pin. The VT pin provides a center-tap for each input (IN, /IN) to a
termination network for maximum interface flexibility. See “Input Interface
Applications” subsection.
2, 3
6, 7
IN0, /IN0
IN1, /IN1
Differential Inputs: These input pairs are the differential signal inputs to the
device. These inputs accept AC- or DC-coupled signals as small as 100mV. The
input pairs internally terminate to a VT pin through 50Ω. Each input has level
shifting resistors of 3.72kΩ to VCC. This allows a wide input voltage range from
VCC to GND. See Figure 3, Simplified Differential Input Stage for details. Note
that these inputs will default to a valid (either HIGH or LOW) state if left open.
See “Input Interface Applications” subsection.
10, 11, 30, 31
GND,
Exposed Pad
Ground. Exposed pad must be connected to a ground plane that is the same
potential as the ground pins.
4
OE
Single-Ended Input: This TTL/CMOS input disables and enables the Q0-Q4
outputs. It is internally connected to a 25kΩ pull-up resistor and will default to a
logic HIGH state if left open. When disabled, Q goes LOW and /Q goes HIGH.
OE being synchronous, outputs will be enabled/disabled following a rising and a
falling edge of the input clock. VTH = VCC/2.
5
SEL
Single-Ended Input: This single-ended TTL/CMOS-compatible input selects the
inputs to the multiplexer. Note that this input is internally connected to a 25kΩ
pull-up resistor and will default to logic HIGH state if left open. VTH = VCC/2.
9, 32
VREF-AC1
VREF-AC0
Reference Voltage: These outputs bias to VCC–1.2V. They are used for AC-
coupling inputs IN and /IN. Connect VREF-AC directly to the corresponding VT
pin. Bypass with 0.01µF low ESR capacitor to VCC. Due to limited drive
capability, the VREF-AC pin is only intended to drive its respective VT pin.
Maximum sink/source current is ±0.5mA. See “Input Interface Applications”
subsection.
12, 13, 16, 19,
22, 25, 28, 29
VCC
Positive Power Supply: Bypass with 0.1µF||0.01µF low ESR capacitors as close
to the VCC pins as possible.
27, 26
24, 23
21, 20
18, 17
15, 14
Q0, /Q0
Q1, /Q1
Q2, /Q2
Q3, /Q3
Q4, /Q4
LVDS Differential Output Pairs: Differential copies of the selected input signal.
The output swing is typically 325mV. Used and unused outputs must be
terminated with 100Ω across the pair (Q, /Q). These differential LVDS outputs
are a logic function of the IN0, IN1, and SEL inputs. See “Truth Table” below.
Truth Table
Inputs
Outputs
IN0
/IN0
IN1
/IN1
SEL
Q
/Q
0
1
X
X
0
0
1
1
0
X
X
0
1
0
X
X
0
1
1
0
1
X
X
1
0
1
1
0




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