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SY89846U 数据表(PDF) 7 Page - Micrel Semiconductor

部件名 SY89846U
功能描述  1.5GHz Precision, LVPECL 1:5 Fanout with 2:1 MUX and Fail Safe Input with Internal Termination
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制造商  MICREL [Micrel Semiconductor]
网页  http://www.micrel.com
标志 MICREL - Micrel Semiconductor

SY89846U 数据表(HTML) 7 Page - Micrel Semiconductor

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Micrel, Inc.
SY89846U
March 2007
M9999-031307-A
hbwhelp@micrel.com or (408) 955-1690
7
Functional Description
Clock Select (SEL)
SEL is an asynchronous TTL/CMOS compatible input
that selects one of the two input signals. An internal
25kΩ pull-up resistor defaults the input to logic HIGH if
left open. Input switching threshold is VCC/2. Refer to
Figure 1a.
Fail-Safe Input (FSI)
The input includes a special fail-safe circuit to sense
the amplitude of the input signal and to latch the
outputs when there is no input signal present, or when
the amplitude of the input signal drops sufficiently
below
100mVPK
(200mVPP),
typically
30mVPK.
Maximum frequency of the SY89846U is limited by the
FSI function. Refer to Figure 1b.
Input Clock Failure Case
If the input clock fails to a floating, static, or extremely
low signal swing such that the voltage swing across
the input pair is significantly less than 100mV, FSI
function will eliminate a metastable condition and latch
the outputs to the last valid state. No ringing and no
undetermined state will occur at the output under
these conditions. The output recovers to normal
operation once the input signal returns to a valid state
with a typical swing greater than 30mV.
Note that the FSI function will not prevent duty cycle
distortion in case of a slowly deteriorating (but still
toggling) input signal. Due to the FSI function, the
propagation delay will depend on rise and fall time of
the input signal and on its amplitude. Refer to “Typical
Operating Characteristics” for detailed information.
Output Enable (OE)
OE is a synchronous TTL/CMOS compatible input that
enables/disables the outputs based on the input to
this pin. The enable function is synchronous so that
the clock outputs will be enabled or disabled following
a rising and a falling edge of the input clock. Refer to
Figure 1c. Internal 25kΩ pull-up resistor defaults the
input to logic HIGH if left open. Input switching
threshold is VCC/2.


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