AD8324

Rev. A | Page 11 of 16

CLK

SDATA

DATEN

TXEN

GND

GND

GND

GND

DATEN

SDATA

CLK

GND

TXEN

RAMP

BYP

SLEEP

NC

GND

AD8324-JRQ

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

1k

Ω

174

Ω

1k

Ω

1k

Ω

1k

Ω

1k

Ω

SLEEP

TO DIPLEXER

TOKO 458PT-1556

10

μF

0.1

μF

0.1

μF

1:1

0.1

μF

0.1

μF

Figure 23. Typical Application Circuit

Table 7. Adjacent Channel Power

Adjacent Channel Symbol Rate (kSym/s)

Channel Symbol Rate (kSym/s)

160

320

640

1280

2560

5120

160

–63

–64

–68

–71

–72

–66

320

–63

–64

–66

–70

–72

–67

640

–64

–64

–65

–67

–71

–67

1280

–67

–65

–65

–66

–68

–67

2560

–70

–67

–66

–66

–67

–65

5120

–72

–70

–67

–67

–64

–64

POWER SUPPLY

a low impedance power bus. This ensures that each pin is at the

same potential. The power bus should be decoupled to ground

using a 10 μF tantalum capacitor located close to the AD8324.

to ground with ceramic chip capacitors located close to the pins.

The bypass pin, labeled BYP, should also be decoupled. The

PCB should have a low impedance ground plane covering all

unused portions of the board, except in areas of the board

where input and output traces are in close proximity to the

AD8324 and the output transformer. All AD8324 ground pins

must be connected to the ground plane to ensure proper

grounding of all internal nodes.

SIGNAL INTEGRITY LAYOUT CONSIDERATIONS

Careful attention to printed circuit board layout details will

prevent problems due to board parasitics. Proper RF design

techniques are mandatory. The differential input and output

traces should be kept as short as possible. Keeping the traces

short will minimize parasitic capacitance and inductance, which

is most critical between the outputs of the AD8324 and the 1:1

output transformer. It is also critical that all differential signal

paths be symmetrical in length and width. In addition, the

input and output traces should be adequately spaced to

minimize coupling (crosstalk) through the board. Following

these guide-lines will optimize the overall performance of the

AD8324 in all applications.

INITIAL POWER-UP

When the supply voltage is first applied to the AD8324, the gain

of the amplifier is initially set to gain code 1. As power is first

applied to the amplifier, the TXEN pin should be held low

(Logic 0) to prevent forward signal transmission. After power

has been applied to the amplifier, the gain can be set to the

desired level by following the procedure provided in the Gain

Programming for the AD8324 section. The TXEN pin can then

be brought from Logic 0 to Logic 1, enabling forward signal

transmission at the desired gain level.

RAMP PIN AND BYP PIN FEATURES

The RAMP pin (Pin 15) is used to control the length of the burst

on and off transients. By default, leaving the RAMP pin

unconnected will result in a transient that is fully compliant with

DOCSIS 2.0 Section 6.2.21.2, Spurious Emissions During Burst

On/Off Transients. DOCSIS requires that all between burst

transients must be dissipated no faster than 2 μs. Adding

capacitance to the RAMP pin will slow the dissipation even more.