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NBSG16VSBAR2 数据表(PDF) 8 Page - ON Semiconductor |
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NBSG16VSBAR2 数据表(HTML) 8 Page - ON Semiconductor |
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8 / 14 page  NBSG16VS http://onsemi.com 8 Table 8. AC CHARACTERISTICS for FCBGA−16 VCC = 0 V; VEE = −3.465 V to −3.0 V or VCC = 3.0 V to 3.465 V; VEE = 0 V Symbol Characteristic −40 °C 25 °C 85 °C Unit Min Typ Max Min Typ Max Min Typ Max fmax Maximum Frequency (See Figure 8) (Note 26) 10.7 (Note 29) 12 10.7 (Note 29) 12 10.7 (Note 29) 12 GHz tPLH, tPHL Propagation Delay to Output Differen- tial (VCTRL = VCC − 2 V) D → Q, Q (VCTRL = VCC − 1 V) D → Q, Q 100 100 125 120 145 140 100 100 125 120 145 140 100 100 125 120 145 140 ps tSKEW Duty Cycle Skew (Note 27) 3 10 3 10 3 10 ps tJITTER RMS Random Clock Jitter fin < 10 GHz Peak−to−Peak Data Dependent Jitter fin < 10 Gb/s 0.8 TBD 2 0.8 TBD 2 0.8 TBD 2 ps VINPP Input Voltage Swing/Sensitivity (Differential Configuration) (Note 28) 75 2600 75 2600 75 2600 mV tr tf Output Rise/Fall Times (20% − 80%) @ 1 GHz (VCTRL = VCC − 2 V) Q, Q (VCTRL = VCC − 1 V) Q, Q 30 30 45 40 55 50 30 30 45 40 55 50 30 30 45 40 55 50 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 26. Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 W to VCC−2.0 V. Input edge rates 40 ps (20% − 80%). 27. tSKEW = |tPLH−tPHL| for a nominal 50% differential clock input waveform. See Figure 10. 28. VINPP(MAX) cannot exceed VCC − VEE (applicable only when VCC − VEE t 2600 mV). 29. Conditions include input amplitude of 500 mV and VCTRL = VCC − 2 V. Minimum output amplitude guarantee of 100 mV (see Output P−P Spec in Figure 8). Table 9. AC CHARACTERISTICS for FCBGA−16 VCC = 0 V; −3.0 V tVEE v −2.375 V or 2.375 V v VCC t 3.0 V; VEE = 0 V Symbol Characteristic −40 °C 25 °C 85 °C Unit Min Typ Max Min Typ Max Min Typ Max fmax Maximum Frequency (See Figure 9) (Note 30) 10.7 (Note 33) 12 10.7 (Note 33) 12 10.7 (Note 33) 12 GHz tPLH, tPHL Propagation Delay to Output Differen- tial (VCTRL = VCC − 2 V) D → Q, Q (VCTRL = VCC − 1 V) D → Q, Q 100 100 125 120 145 140 100 100 125 120 145 140 100 100 125 120 145 140 ps tSKEW Duty Cycle Skew (Note 31) 3 10 3 10 3 10 ps tJITTER RMS Random Clock Jitter fin < 10 GHz Peak−to−Peak Data Dependent Jitter fin < 10 Gb/s 0.9 TBD 3 0.9 TBD 3 0.9 TBD 3 ps VINPP Input Voltage Swing/Sensitivity (Differential Configuration) (Note 32) 75 2600 75 2600 75 2600 mV tr tf Output Rise/Fall Times (20% − 80%) @ 1 GHz (VCTRL = VCC − 2 V) Q, Q (VCTRL = VCC − 1 V) Q, Q 25 22 50 45 70 60 25 22 50 45 70 60 25 22 50 45 70 60 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 30. Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 W to VCC−2.0 V. Input edge rates 40 ps (20% − 80%). 31. tSKEW = |tPLH−tPHL| for a nominal 50% differential clock input waveform. See Figure 10. 32. VINPP(MAX) cannot exceed VCC − VEE (applicable only when VCC − VEE t 2600 mV). 33. Conditions include input amplitude of 500 mV and VCTRL = VCC − 2 V. Minimum output amplitude guarantee of 100 mV (see Output P−P Spec in Figure 9). |
类似零件编号 - NBSG16VSBAR2 |
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类似说明 - NBSG16VSBAR2 |
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