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MC33560DWR2G 数据表(PDF) 4 Page - ON Semiconductor |
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MC33560DWR2G 数据表(HTML) 4 Page - ON Semiconductor |
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4 / 26 page  MC33560 http://onsemi.com 4 ELECTRICAL CHARACTERISTICS (continued) These specifications are written in the same style as common for standard integrated circuits. The convention considers current flowing into the pin (sink current) as positive and current flowing out of the pin (source current) as negative. (Conditions: VBAT = 4.0 V, VCC = 5.0 V nom, PWRON = VBAT , Operating Mode, −ICC = 10 mA, −25°C ≤ TA ≤ 85°C, L1 = 47 mH, RLIM = 0 W, CRDVCC capacitor = 10 mF, unless otherwise noted.) Characteristic Unit Max Typ Min Symbol Test Conditions APPLICATION INTERFACE DC SECTION (VBAT = 5.0 V) Input High Threshold Voltage (increasing) Pins 2, 4, 5, 6, 10, 17 VIH 0.55*VBAT − 0.65*VBAT V Input Low Threshold Voltage (decreasing) Pins 2, 5, 6, 10 Pin 17 Pin 4 VIL 0.3*VBAT 0.2*VBAT 0.3*VBAT − − − 0.45*VBAT 0.40*VBAT 0.5*VBAT V Switching Hysteresis Pins 2, 4, 5, 6, 10, 17 VHYST 0.06*VBAT − 0.3*VBAT V Threshold Voltage Pin 9 Pin 18 VTH 0.5*VBAT 0.4*VBAT − − 0.6*VBAT 0.6*VBAT V Pulldown resistance VIN = VBAT − 1.0 V, Pins 2, 6, 7, 10 Rdown 120 240 500 k W Pullup resistance VIN = 0.5 V, Pin 3, 4, 5 Rup 120 240 500 k W Output High Voltage IOH = −2.5 mA, Pin 3, Pin 4 for CS = H IOH = −50 mA, pins 7, 20,21 IOH = −0.2 mA, Pin 8 Pin 4 ( in Output Mode) VOH VBAT − 1 − − V Output Low Voltage IOL = 1.0 mA, Pins 7, 20, 21 IOL = 0.2 mA, Pins 3, 4, 8 VOL − − 0.4 V Input Leakage Current VIN = 2.5 V, CS = H, Pins 9, 17, 18, 20, 21 ±Ileak − − 2.0 mA CARD INTERFACE DC SECTION (VBAT = 5.0 V) Output High Voltage IOH = −20 mA, Pins 11, 16, 19 IOL = 0.2 mA, Pins 14, 15 VOH VCC − 0.9 − − V Output Low Voltage IOL = 1.0 mA, Pins 11, 16, 19 IOL = 0.2 mA, Pins 14, 15 VOL − − 0.4 V I/O Pullup Resistance, Operating Mode, CS =L , PWRON = H VOL = 0.5 V, Pins 11, 16, 19 − − 18 − k W Card pins security voltage (Card access deactivated) PWRON = GND, lin = 10 mA, Pins 11, 14, 15, 16, 19 Vsecurity − − 2.0 V DIGITAL DYNAMIC SECTION (VBAT = 5.0 V, Normal Operating Mode) (Note 6) Input Clock Frequency Pin 9, Duty Cycle = 50% fasyclk − − 20 MHz Card Clock Frequency Pin 15 fcrdclk − − 20 MHz Card Clock Duty Cycle (Note 7) Pin 15, 50% to 50% VCC, fio = 16 MHz rclk 45 − 55 % Card Clock Rise and Fall Time Pin 15, 10% ↔ 90% VCC trclk, tfclk − − 10 ns I/O Data Transfer Frequency Pin [7, 11], [21, 16], [20, 19] (Note 8) fio − 1.0 − MHz I/O Duty Cycle Pin [7, 11], [21, 16], [20, 19] (Note 8) 50% to 50% VCC rio 45 − 55 % I/O Rise and Fall Time Pin [7, 11], [21, 16], [20, 19] (Note 8) 10% ↔ 90% VCC trio, tfio − − 150 ns I/O Transfer Time Pin [7, 11], [21, 16], [20, 19] (Note 8) 50% to 50% VCC, L → H, H → L ttr − − 100 ns Card Signal Sequence Interval Pins 11, 14, 15, 16, 19 VCC Powerup / Powerdown tdseq − 0.2 1.0 ms 4. See Figures 2 and 3. 5. The transistors T1 on lines IO, C4 and C8 (see Figure 24) have a max Rdson of 250 W. 6. Pin loading = 30 pF, except INVOUT = 15 pF. 7. As the clock buffer is optimized for low power consumption and hence not symmetrical, clock signal duty cycle is guaranteed for divide by 2 and divide by 4 ratio. 8. In either direction. |
类似零件编号 - MC33560DWR2G |
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类似说明 - MC33560DWR2G |
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