© Semiconductor Components Industries, LLC, 2006

January, 2006 − Rev. 5

1

Publication Order Number:

MC14518B/D

MC14518B, MC14520B

Dual Up Counters

The MC14518B dual BCD counter and the MC14520B dual binary

counter are constructed with MOS P−channel and N−channel

enhancement mode devices in a single monolithic structure. Each

consists of two identical, independent, internally synchronous 4−stage

counters. The counter stages are type D flip−flops, with interchangeable

Clock and Enable lines for incrementing on either the positive−going or

negative−going transition as required when cascading multiple stages.

Each counter can be cleared by applying a high level on the Reset line.

In addition, the MC14518B will count out of all undefined states within

two clock periods. These complementary MOS up counters find

primary use in multi−stage synchronous or ripple counting applications

requiring low power dissipation and/or high noise immunity.

Features

of Clock or Negative Transition on Enable

Schottky TTL Load Over the Rated Temperature Range

Symbol

Parameter

Value

Unit

DC Supply Voltage Range

− 0.5 to +18.0

V

Input or Output Voltage Range

(DC or Transient)

V

Input or Output Current

(DC or Transient) per Pin

±10

mA

Power Dissipation,

per Package (Note 2.)

500

mW

Operating Temperature Range

− 55 to +125

°C

Storage Temperature Range

− 65 to +150

°C

Lead Temperature

(8−Second Soldering)

260

°C

Maximum ratings are those values beyond which device damage can occur.

Maximum ratings applied to the device are individual stress limit values (not

normal operating conditions) and are not valid simultaneously. If these limits are

exceeded, device functional operation is not implied, damage may occur and

reliability may be affected.

1. Maximum Ratings are those values beyond which damage to the device

may occur.

2. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/

_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

Unused inputs must always be tied to an appropriate logic voltage level (e.g.,

http://onsemi.com

xx

= 18 or 20

A

= Assembly Location

WL, L

= Wafer Lot

YY, Y

= Year

WW, W

= Work Week

G

= Pb−Free Indicator

MARKING

DIAGRAMS

1

16

PDIP−16

P SUFFIX

CASE 648

MC145xxBCP

AWLYYWWG

SOIC−16

DW SUFFIX

CASE 751G

1

16

145xxB

AWLYYWWG

SOEIAJ−16

F SUFFIX

CASE 966

1

16

MC145xxB

ALYWG

See detailed ordering and shipping information in the package

dimensions section on page 7 of this data sheet.

ORDERING INFORMATION