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MC10LVEL40DWR2 数据表(PDF) 1 Page - ON Semiconductor

部件名 MC10LVEL40DWR2
功能描述  3.3/5V ECL Differential Phase?묯requency Detector
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制造商  ONSEMI [ON Semiconductor]
网页  http://www.onsemi.com
标志 ONSEMI - ON Semiconductor

MC10LVEL40DWR2 数据表(HTML) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 8
1
Publication Order Number:
MC100LVEL40/D
MC100LVEL40
3.3/5VECL Differential
Phase−Frequency Detector
Description
The MC100LVEL40 is a three state phase frequency−detector
intended for phase−locked loop applications which require a minimum
amount of phase and frequency difference at lock. Advanced design
significantly reduces the dead zone of the detector. For proper
operation, the input edge rate of the R and V inputs should be less than
5 ns. The device is designed to work with a 3.3 V power supply.
When the reference (R) and the feedback (FB) inputs are unequal in
frequency and/or phase the differential up (U) and down (D) outputs
will provide pulse streams which when subtracted and integrated
provide an error voltage for control of a VCO.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
For application information, refer to AND8040/D, “Phase Lock
Loop Operation.”
The 100 Series Contains Temperature Compensation
Features
250 MHz Typical Bandwidth
PECL Mode Operating Range:
VCC = 3.0 V to 5.5 V with VEE = 0 V
NECL Mode Operating Range:
VCC = 0 V with VEE = −3.0 V to −5.5 V
Internal Input Pulldown Resistor
Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
MARKING
DIAGRAM
SO−20
DW SUFFIX
CASE 751D
1
20
http://onsemi.com
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
20
1
100LVEL40
AWLYYWWG


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