CAT24C256

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Doc. No. 04, Rev. D

© 2007 by Catalyst Semiconductor, Inc.

Characteristics subject to change without notice

READ OPERATIOnS

Immediate Address Read

In standby mode, the CAT24C256 internal address

counter points to the data byte immediately following the

last byte accessed by a previous operation. If that ‘previ-

ous’ byte was the last byte in memory, then the address

When, following a START, the CAT24C256 is presented

with a Slave address containing a ‘’ in the R/W bit

clock cycle, and will then transmit data being pointed

at by the internal address counter. The Master can stop

further transmission by issuing a NoACK, followed by a

STOP condition.

Selective Read

The Read operation can also be started at an address

different from the one stored in the internal address

counter. The address counter can be initialized by per-

forming a ‘dummy’ Write operation (Figure 9). Here the

START is followed by the Slave address (with the R/W

bit set to ‘0’) and the desired two byte address. Instead

START, followed by the ‘Immediate Address Read’ se-

quence, as described earlier.

Sequential Read

by the CAT24C256, then the device will continue trans-

mitting as long as each data byte is acknowledged by

the Master (Figure 0). If the end of memory is reached

during sequential Read, then the address counter will

‘wrap-around’tothebeginningofmemory,etc.Sequential

Read works with either ‘Immediate Address Read’ or

‘Selective Read’, the only difference being the starting

byte address.