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ADSP-21367BBP-2A 数据表(PDF) 8 Page - Analog Devices |
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ADSP-21367BBP-2A 数据表(HTML) 8 Page - Analog Devices |
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8 / 56 page  Rev. A | Page 8 of 56 | August 2006 ADSP-21367/ADSP-21368/ADSP-21369 Serial ports operate in five modes: • Standard DSP serial mode •Multichannel (TDM) mode with support for packed I2S mode •I2S mode •Packed I2S mode • Left-justified sample pair mode Left-justified sample pair mode is a mode where in each frame sync cycle two samples of data are transmitted/received—one sample on the high segment of the frame sync, the other on the low segment of the frame sync. Programs have control over var- ious attributes of this mode. Each of the serial ports supports the left-justified sample pair and I2S protocols (I2S is an industry-standard interface com- monly used by audio codecs, ADCs, and DACs such as the Analog Devices AD183x family), with two data pins, allowing four left-justified sample pair or I2S channels (using two stereo devices) per serial port, with a maximum of up to 32 I2S chan- nels. The serial ports permit little-endian or big-endian transmission formats and word lengths selectable from 3 bits to 32 bits. For the left-justified sample pair and I2S modes, data- word lengths are selectable between 8 bits and 32 bits. Serial ports offer selectable synchronization and transmit modes as well as optional μ-law or A-law companding selection on a per channel basis. Serial port clocks and frame syncs can be inter- nally or externally generated. The serial ports also contain frame sync error detection logic where the serial ports detect frame syncs that arrive early (for example, frame syncs that arrive while the transmission/recep- tion of the previous word is occurring). All the serial ports also share one dedicated error interrupt. S/PDIF-Compatible Digital Audio Receiver/Transmitter and Synchronous/Asynchronous Sample Rate Converter The S/PDIF receiver/transmitter has no separate DMA chan- nels. It receives audio data in serial format and converts it into a biphase encoded signal. The serial data input to the receiver/transmitter can be formatted as left-justified, I2S, or right-justified with word widths of 16, 18, 20, or 24 bits. The serial data, clock, and frame sync inputs to the S/PDIF receiver/transmitter are routed through the signal routing unit (SRU). They can come from a variety of sources such as the SPORTs, external pins, the precision clock generators (PCGs), or the sample rate converters (SRC) and are controlled by the SRU control registers. The sample rate converter (SRC) contains four SRC blocks and is the same core as that used in the AD1896 192 kHz stereo asynchronous sample rate converter and provides up to 128 dB SNR. The SRC block is used to perform synchronous or asyn- chronous sample rate conversion across independent stereo channels, without using internal processor resources. The four SRC blocks can also be configured to operate together to con- vert multichannel audio data without phase mismatches. Finally, the SRC can be used to clean up audio data from jittery clock sources such as the S/PDIF receiver. Digital Peripheral Interface (DPI) The digital peripheral interface provides connections to two serial peripheral interface ports (SPI), two universal asynchro- nous receiver-transmitters (UARTs), a two-wire interface (TWI), 12 flags, and three general-purpose timers. Serial Peripheral (Compatible) Interface The processors contain two serial peripheral interface ports (SPIs). The SPI is an industry-standard synchronous serial link, enabling the SPI-compatible port to communicate with other SPI-compatible devices. The SPI consists of two data pins, one device select pin, and one clock pin. It is a full-duplex synchro- nous serial interface, supporting both master and slave modes. The SPI port can operate in a multimaster environment by interfacing with up to four other SPI-compatible devices, either acting as a master or slave device. The ADSP-21367/ ADSP-21368/ADSP-21369 SPI-compatible peripheral imple- mentation also features programmable baud rate and clock phase and polarities. The SPI-compatible port uses open drain drivers to support a multimaster configuration and to avoid data contention. UART Port The processors provide a full-duplex universal asynchronous receiver/transmitter (UART) port, which is fully compatible with PC-standard UARTs. The UART port provides a simpli- fied UART interface to other peripherals or hosts, supporting full-duplex, DMA-supported, asynchronous transfers of serial data. The UART also has multiprocessor communication capa- bility using 9-bit address detection. This allows it to be used in multidrop networks through the RS-485 data interface stan- dard. The UART port also includes support for five data bits to eight data bits, one stop bit or two stop bits, and none, even, or odd parity. The UART port supports two modes of operation: • PIO (programmed I/O) – The processor sends or receives data by writing or reading I/O-mapped UART registers. The data is double-buffered on both transmit and receive. • DMA (direct memory access) – The DMA controller trans- fers both transmit and receive data. This reduces the number and frequency of interrupts required to transfer data to and from memory. The UART has two dedicated DMA channels, one for transmit and one for receive. These DMA channels have lower default priority than most DMA channels because of their relatively low service rates. The UART port’s baud rate, serial data format, error code gen- eration and status, and interrupts are programmable: • Supporting bit rates ranging from (fSCLK/ 1,048,576) to (fSCLK/16) bits per second. • Supporting data formats from 7 bits to 12 bits per frame. • Both transmit and receive operations can be configured to generate maskable interrupts to the processor. Where the 16-bit UART_Divisor comes from the DLH register (most significant eight bits) and DLL register (least significant eight bits). |
类似零件编号 - ADSP-21367BBP-2A |
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类似说明 - ADSP-21367BBP-2A |
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