MC74HC244A

http://onsemi.com

5

TEST CIRCUITS

*Includes all probe and jig capacitance

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

Figure 3. Test Circuit

*Includes all probe and jig capacitance

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

Figure 4. Test Circuit

CONNECT TO GND WHEN

1 kW

PIN DESCRIPTIONS

INPUTS

A1, A2, A3, A4, B1, B2, B3, B4

(Pins 2, 4, 6, 8, 11, 13, 15, 17)

Data input pins. Data on these pins appear in noninverted

form on the corresponding Y outputs, when the outputs are

enabled.

CONTROLS

Enable A, Enable B (Pins 1, 19)

Output enables (active−low). When a low level is applied

to these pins, the outputs are enabled and the devices

function as noninverting buffers. When a high level is

applied, the outputs assume the high impedance state.

OUTPUTS

YA1, YA2, YA3, YA4, YB1, YB2, YB3, YB4

(Pins 18, 16, 14, 12, 9, 7, 5, 3)

Device outputs. Depending upon the state of the

output−enable pins, these outputs are either noninverting

outputs or high−impedance outputs.

LOGIC DETAIL

DATA

INPUT

A OR B

ENABLE A OR

ENABLE B

TO THREE OTHER

A OR B INVERTERS

ONE OF 8

INVERTERS

YA

OR

YB