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MC10EP446 数据表(PDF) 2 Page - ON Semiconductor |
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MC10EP446 数据表(HTML) 2 Page - ON Semiconductor |
2 / 20 page MC10EP446, MC100EP446 http://onsemi.com 2 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 1 234567 8 24 23 22 21 20 19 18 17 16 Figure 1. LQFP−32 Pinout (Top View) Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. VCC SOUT VEE VBB2 VEF VEE PCLK PCLK SOUT VCF SYNC SYNC VCC VCC VCC VCC MC10EP446 MC100EP446 Figure 2. QFN−32 Pinout (Top View) 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 1 2 34 5 6 78 24 23 22 21 20 19 18 17 Exposed Pad (EP) SOUT VEE PCLK PCLK SOUT VCC VCC VCC VCC VEE VBB2 VEF VCF SYNC SYNC VCC Table 1. PIN DESCRIPTION PIN FUNCTION D0*−D7* ECL, CMOS, or TTL Parallel Data Input SOUT, SOUT ECL Differential Serial Data Output CLK*, CLK* ECL Differential Clock Input PCLK, PCLK ECL Differential Parallel Clock Output SYNC*, SYNC** ECL Conversion Synchronizing Differential Input (Reset)*** CKSEL* ECL Clock Input Selector CKEN*, CKEN* ECL Clock Enable Differential Input VCF ECL, CMOS, or TTL Input Selector VEF ECL Reference Mode Connection VBB1, VBB2 Reference Voltage Output VCC Positive Supply VEE Negative Supply * Pins will default LOW when left open. **Pins will default HIGH when left open. ***The rising edge of SYNC will asynchronously reset the internal circuitry. The falling edge of the SYNC followed by the falling edge of CLK initiates the conversion process synchronously on the next rising edge of CLK. |
类似零件编号 - MC10EP446_07 |
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类似说明 - MC10EP446_07 |
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