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MC100E446FNR2G 数据表(PDF) 7 Page - ON Semiconductor |
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MC100E446FNR2G 数据表(HTML) 7 Page - ON Semiconductor |
7 / 12 page MC10E446, MC100E446 http://onsemi.com 7 Table 8. AC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V or VCCx = 0.0 V; VEE = −5.0 V (Note 9) Symbol Characteristic 0°C 25°C 85°C Unit Min Typ Max Min Typ Max Min Typ Max FMAX Max Conversion Frequency 1.3 1.6 1.3 1.6 1.3 1.6 Gb/s NRZ tPLH tPHL Propagation Delay to Output CLK to SOUT (Note 10) CLK to CL/4 CLK to CL/8 SYNC to CL/4, CL/8 1020 650 800 650 1200 850 1050 850 1480 1050 1300 1100 1020 650 800 650 1200 850 1050 850 1480 1050 1300 1100 1020 650 800 650 1200 850 1050 850 1480 1050 1300 1100 ps ts Setup Time (Note 11) SIN, Dn -200 -450 -200 −450 −200 −450 ps th Hold Time (Note 11) SIN, Dn 900 650 900 650 900 650 ps tRR Reset Recovery Time SYNC 500 300 500 300 500 300 ps tPW Min Pulse Width CLK, MR 300 300 300 ps tJITTER Random Clock Jitter (RMS) < 1 < 1 < 1 ps VPP Input Voltage Swing (Differential Configuration) 150 1000 150 1000 150 1000 mV tr tf Rise/Fall Times (20% - 80%) SOUT Other 100 200 225 425 350 650 100 200 225 425 350 650 100 200 225 425 350 650 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 9. 10 Series: VEE can vary −0.46 V / +0.06 V. 100 Series: VEE can vary −0.46 V / +0.8 V. 10.Propagation delays measured from negative going clock edge. 11. Relative to negative clock edge. CLK D th ts Valid Data Setup Hold CLK SYNC trr Figure 3. |
类似零件编号 - MC100E446FNR2G |
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类似说明 - MC100E446FNR2G |
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