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MC100E196FNR2G 数据表(PDF) 8 Page - ON Semiconductor |
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MC100E196FNR2G 数据表(HTML) 8 Page - ON Semiconductor |
8 / 12 page MC10E196, MC100E196 http://onsemi.com 8 When the SET MAX pin of chip #1 is asserted the D0 and D1 latches will be reset while the rest of the latches will be set. In addition, to maintain monotonicity an additional gate delay is selected in the cascade circuitry. As a result when D7 of chip #1 is asserted the delay increases from 31.75 gates to 32 gates. A 32 gate delay is the maximum delay setting for the E196. When cascading multiple PDC’s it will prove more cost effective to use a single E196 for the Most Significant Bit (MSB) of the chain while using E195 for the lower order bits. This is due to the fact that only one fine tune input is needed to further reduce the delay step resolution. ADDRESS BUS (A0−A6) A7 INPUT D1 D0 LEN VEE IN IN VBB VCC VCC0 Q Q VCC0 D1 D0 LEN VEE IN IN VBB VCC VCC0 Q Q VCC0 OUTPUT E196 Chip #1 E196 Chip #2 Figure 3. Cascading Interconnect Architecture FTUNE LINEAR INPUT FTUNE SET MIN SET MAX TO SELECT MULTIPLEXERS BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 D0 Q0 LEN Reset Reset D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 LEN LEN LEN LEN LEN LEN LEN CASCADE CASCADE Figure 4. Expansion of the Latch Section of the E196 Block Diagram Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset |
类似零件编号 - MC100E196FNR2G |
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类似说明 - MC100E196FNR2G |
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