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MAX3000A_06 Datasheet(数据表) 36 Page - Altera Corporation

部件型号  MAX3000A
说明  Programmable Logic Device Family
下载  46 Pages
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation

MAX3000A Datasheet(HTML) 36 Page - Altera Corporation

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Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
tZX3
Output buffer enable delay, slow
slew rate = on
VCCIO = 2.5 V or 3.3 V
C1 = 35 pF
9.0
10.0
ns
tXZ
Output buffer disable delay
C1 = 5 pF
4.0
5.0
ns
tSU
Register setup time
2.1
2.9
ns
tH
Register hold time
0.9
1.2
ns
tRD
Register delay
1.2
1.6
ns
tCOMB
Combinatorial delay
0.8
1.2
ns
tIC
Array clock delay
1.6
2.1
ns
tEN
Register enable time
1.0
1.3
ns
tGLOB
Global control delay
1.5
2.0
ns
tPRE
Register preset time
2.3
3.0
ns
tCLR
Register clear time
2.3
3.0
ns
tPIA
PIA delay
(2)
2.4
3.2
ns
tLPA
Low–power adder
(5)
4.0
5.0
ns
Table 24. EPM3512A External Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-7
-10
Min
Max
Min
Max
tPD1
Input to non-registered output
C1 = 35 pF (2)
7.5
10.0
ns
tPD2
I/O input to non-registered
output
C1 = 35 pF (2)
7.5
10.0
ns
tSU
Global clock setup time
(2)
5.6
7.6
ns
tH
Global clock hold time
(2)
0.0
0.0
ns
tFSU
Global clock setup time of fast
input
3.0
3.0
ns
tFH
Global clock hold time of fast
input
0.0
0.0
ns
tCO1
Global clock to output delay
C1 = 35 pF
1.0
4.7
1.0
6.3
ns
tCH
Global clock high time
3.0
4.0
ns
tCL
Global clock low time
3.0
4.0
ns
tASU
Array clock setup time
(2)
2.5
3.5
ns
Table 23. EPM3256A Internal Timing Parameters (Part 2 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
–7
–10
Min
Max
Min
Max




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