数据搜索系统,热门电子元器件搜索
  Chinese▼

Delete All
ON OFF
ALLDATASHEETCN.COM

X  

预览 PDF Download HTML

MAX3000A_06 Datasheet(数据表) 29 Page - Altera Corporation

部件型号  MAX3000A
说明  Programmable Logic Device Family
下载  46 Pages
Scroll/Zoom Zoom In 100% Zoom Out
制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation

MAX3000A Datasheet(HTML) 29 Page - Altera Corporation

Back Button MAX3000A_06 数据表 HTML 25Page - Altera Corporation MAX3000A_06 数据表 HTML 26Page - Altera Corporation MAX3000A_06 数据表 HTML 27Page - Altera Corporation MAX3000A_06 数据表 HTML 28Page - Altera Corporation MAX3000A_06 数据表 HTML 29Page - Altera Corporation MAX3000A_06 数据表 HTML 30Page - Altera Corporation MAX3000A_06 数据表 HTML 31Page - Altera Corporation MAX3000A_06 数据表 HTML 32Page - Altera Corporation MAX3000A_06 数据表 HTML 33Page - Altera Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 29 page
background image
Altera Corporation
29
MAX 3000A Programmable Logic Device Family Data Sheet
Table 17. EPM3032A Internal Timing Parameters (Part 1 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
–4
–7
–10
Min
Max
Min
Max
Min
Max
tIN
Input pad and buffer delay
0.7
1.2
1.5
ns
tIO
I/O input pad and buffer
delay
0.7
1.2
1.5
ns
tSEXP
Shared expander delay
1.9
3.1
4.0
ns
tPEXP
Parallel expander delay
0.5
0.8
1.0
ns
tLAD
Logic array delay
1.5
2.5
3.3
ns
tLAC
Logic control array delay
0.6
1.0
1.2
ns
tIOE
Internal output enable delay
0.0
0.0
0.0
ns
tOD1
Output buffer and pad
delay, slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF
0.8
1.3
1.8
ns
tOD2
Output buffer and pad
delay, slow slew rate = off
VCCIO = 2.5 V
C1 = 35 pF
1.3
1.8
2.3
ns
tOD3
Output buffer and pad
delay, slow slew rate = on
VCCIO = 2.5 V or 3.3 V
C1 = 35 pF
5.8
6.3
6.8
ns
tZX1
Output buffer enable delay,
slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF
4.0
4.0
5.0
ns
tZX2
Output buffer enable delay,
slow slew rate = off
VCCIO = 2.5 V
C1 = 35 pF
4.5
4.5
5.5
ns
tZX3
Output buffer enable delay,
slow slew rate = on
VCCIO = 2.5 V or 3.3 V
C1 = 35 pF
9.0
9.0
10.0
ns
tXZ
Output buffer disable delay C1 = 5 pF
4.0
4.0
5.0
ns
tSU
Register setup time
1.3
2.0
2.8
ns
tH
Register hold time
0.6
1.0
1.3
ns
tRD
Register delay
0.7
1.2
1.5
ns
tCOMB
Combinatorial delay
0.6
1.0
1.3
ns
tIC
Array clock delay
1.2
2.0
2.5
ns
tEN
Register enable time
0.6
1.0
1.2
ns
tGLOB
Global control delay
0.8
1.3
1.9
ns
tPRE
Register preset time
1.2
1.9
2.6
ns
tCLR
Register clear time
1.2
1.9
2.6
ns




HTML 页

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46 


数据表 下载

Go To PDF Page

相关电子零件

部件型号部件说明Html View制造商
APEX20KProgrammable Logic Device Family 1 2 3 4 5 MoreAltera Corporation
ISP1016EHigh-Density Programmable Logic 1 2 3 4 5 MoreLattice Semiconductor
PLUS173-10Programmable logic array 22 x 42 x 10 1 2 3 4 5 MoreNXP Semiconductors
PAL1016P83ns ECL ASPECT Programmable Array Logic 1 2 3 4 5 MoreNational Semiconductor (TI)
RXE010PolySwitch RXE device 1 2 3 4 5 MoreList of Unclassifed Manufacturers
Z86L7103ZEMICEBOX FAMILY IN-CIRCUIT EMULATOR-L71 1 2 3 4 5 MoreZilog, Inc.
TMPR492564-Bit TX System RISC TX49 Family 1 2 3 4 5 MoreToshiba Semiconductor
PHD36N03LTN-channel TrenchMOS logic level FET 1 2 3 4 5 MoreNXP Semiconductors
FDS6690ASingle N-Channel Logic Level PowerTrenchTM MOSFET 1 2 3 4 5 MoreFairchild Semiconductor

链接网址


Privacy Policy
ALLDATASHEETCN.COM
ALLDATASHEET是否为您带来帮助?  [ DONATE ]  

关于 Alldatasheet    |   广告服务   |   联系我们   |   隐私政策   |   书签   |   链接交换   |   制造商名单
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  , Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp  |   Russian : Alldatasheetru.com
Korean : Alldatasheet.co.kr   |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com  |   Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl