MAX3000A_06 Datasheet(数据表) 14 Page

14 page

Altera Corporation

MAX 3000A Programmable Logic Device Family Data Sheet

Programming Sequence

During in-system programming, instructions, addresses, and data are

shifted into the MAX 3000A device through the TDI input pin. Data is

shifted out through the TDO output pin and compared against the

expected data.

Programming a pattern into the device requires the following six ISP

stages. A stand-alone verification of a programmed pattern involves only

stages 1, 2, 5, and 6.

Enter ISP. The enter ISP stage ensures that the I/O pins transition

smoothly from user mode to ISP mode. The enter ISP stage requires

1ms.

Check ID. Before any program or verify process, the silicon ID is

checked. The time required to read this silicon ID is relatively small

compared to the overall programming time.

Bulk Erase. Erasing the device in-system involves shifting in the

instructions to erase the device and applying one erase pulse of

100 ms.

Program. Programming the device in-system involves shifting in the

address and data and then applying the programming pulse to

program the EEPROM cells. This process is repeated for each

EEPROM address.

Verify. Verifying an Altera device in-system involves shifting in

addresses, applying the read pulse to verify the EEPROM cells, and

shifting out the data for comparison. This process is repeated for

each EEPROM address.

Exit ISP. An exit ISP stage ensures that the I/O pins transition

smoothly from ISP mode to user mode. The exit ISP stage requires

1ms.

Programming Times

The time required to implement each of the six programming stages can

be broken into the following two elements:

■

A pulse time to erase, program, or read the EEPROM cells.

■

A shifting time based on the test clock (TCK) frequency and the

number of TCK cycles to shift instructions, address, and data into the

device.

MAX3000A_06 Datasheet(数据表) 14 Page - Altera Corporation

MAX3000A Datasheet(HTML) 14 Page - Altera Corporation

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