DTC115EET1G datasheet(1/11 Pages) ONSEMI

部件名	DTC115EET1G

功能描述	Bias Resistor Transistor NPN Silicon Surface Mount Transistor with Monolithic Bias Resistor Network

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制造商	ONSEMI [ON Semiconductor]

网页	http://www.onsemi.com

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March, 2006 − Rev. 8

1

Publication Order Number:

DTC114EET1/D

DTC114EET1 Series

Bias Resistor Transistor

NPN Silicon Surface Mount Transistor

with Monolithic Bias Resistor Network

This new series of digital transistors is designed to replace a single

device and its external resistor bias network. The BRT (Bias Resistor

Transistor) contains a single transistor with a monolithic bias network

consisting of two resistors; a series base resistor and a base−emitter

resistor. The BRT eliminates these individual components by

integrating them into a single device. The use of a BRT can reduce

both system cost and board space. The device is housed in the

SC−75/SOT−416 package which is designed for low power surface

mount applications.

Features

• Simplifies Circuit Design

• Reduces Board Space

• Reduces Component Count

• The SC−75/SOT−416 Package Can be Soldered Using Wave or

Reflow

• The Modified Gull−Winged Leads Absorb Thermal Stress During

Soldering Eliminating the Possibility of Damage to the Die

• Pb−Free Packages are Available

MAXIMUM RATINGS (TA = 25°C unless otherwise noted)

Rating

Symbol

Value

Unit

Collector-Base Voltage

VCBO

50

Vdc

Collector-Emitter Voltage

VCEO

50

Vdc

Collector Current

IC

100

mAdc

THERMAL CHARACTERISTICS

Rating

Symbol

Value

Unit

Total Device Dissipation,

FR−4 Board (Note 1) @ TA = 25°C

Derate above 25

°C

PD

200

1.6

mW

mW/

°C

Thermal Resistance,

Junction−to−Ambient (Note 1)

RqJA

600

°C/W

Total Device Dissipation,

FR−4 Board (Note 2) @ TA = 25°C

Derate above 25

°C

PD

300

2.4

mW

mW/

°C

Thermal Resistance,

Junction−to−Ambient (Note 2)

RqJA

400

°C/W

Junction and Storage Temperature

Range

TJ, Tstg

−55 to +150

°C

Stresses exceeding Maximum Ratings may damage the device. Maximum

Ratings are stress ratings only. Functional operation above the Recommended

Operating Conditions is not implied. Extended exposure to stresses above the

Recommended Operating Conditions may affect device reliability.

1. FR−4 @ Minimum Pad

2. FR−4 @ 1.0

× 1.0 Inch Pad

NPN SILICON

BIAS RESISTOR TRANSISTORS

PIN 3

COLLECTOR

(OUTPUT)

PIN 2

EMITTER

(GROUND)

PIN 1

BASE

(INPUT)

R1

R2

See detailed ordering, marking, and shipping information in

the package dimensions section on page 2 of this data sheet.

ORDERING INFORMATION

http://onsemi.com

SC−75 (SOT−416)

CASE 463

STYLE 1

3

2

1

MARKING DIAGRAM

xx M

G

xx

= Specific Device Code

xx = (Refer to page 2)

M

= Date Code*

G

= Pb−Free Package

(Note: Microdot may be in either location)

*Date Code orientation may vary depending

upon manufacturing location.

类似零件编号 - DTC115EET1G

制造商	部件名	数据表	功能描述
ON Semiconductor	DTC115EET1G	102Kb / 10P	Bias Resistor Transistor January, 2005 ??Rev. 6
	DTC115EET1G	121Kb / 9P	Digital Transistors (BRT) R1 = 100 k, R2 = 100 k August, 2012 ??Rev. 0
	DTC115EET1G	145Kb / 13P	Bias Resistor Transistor NPN Silicon Surface Mount Transistor with Monolithic Bias Resistor Network May, 2012 ??Rev. 12
	DTC115EET1G	136Kb / 10P	Digital Transistors (BRT) R1 = 100 k, R2 = 100 k February, 2013 ??Rev. 2
	DTC115EET1G	125Kb / 10P	Digital Transistors (BRT) November, 2016 ??Rev. 3

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