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SN74LVC125ADR 数据表(PDF) 1 Page - Texas Instruments |
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SN74LVC125ADR 数据表(HTML) 1 Page - Texas Instruments |
1 / 12 page SN74LVC125A QUADRUPLE BUS BUFFER GATE WITH 3STATE OUTPUTS SCAS290N − JANUARY 1993 − REVISED FEBRUARY 2004 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Operates From 1.65 V to 3.6 V D Specified From −40°C to 85°C and −40 °C to 125°C D Inputs Accept Voltages to 5.5 V D Max tpd of 4.8 ns at 3.3 V D Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C D Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C D Latch-Up Performance Exceeds 250 mA Per JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) description/ordering information This quadruple bus buffer gate is designed for 1.65-V to 3.6-V VCC operation. The SN74LVC125A features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING −40 °C to 85°C QFN − RGY Reel of 1000 SN74LVC125ARGYR LC125A Tube of 50 SN74LVC125AD SOIC − D Reel of 2500 SN74LVC125ADR LVC125A SOIC − D Reel of 250 SN74LVC125ADT LVC125A −40 °C to 125°C SOP − NS Reel of 2000 SN74LVC125ANSR LVC125A −40 °C to 125°C SSOP − DB Reel of 2000 SN74LVC125ADBR LC125A Tube of 90 SN74LVC125APW TSSOP − PW Reel of 2000 SN74LVC125APWR LC125A TSSOP − PW Reel of 250 SN74LVC125APWT LC125A † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Copyright 2004, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. D, DB, NS, OR PW PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 14 13 12 11 10 9 8 1OE 1A 1Y 2OE 2A 2Y GND VCC 4OE 4A 4Y 3OE 3A 3Y RGY PACKAGE (TOP VIEW) 114 78 2 3 4 5 6 13 12 11 10 9 4OE 4A 4Y 3OE 3A 1A 1Y 2OE 2A 2Y |
类似零件编号 - SN74LVC125ADR |
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类似说明 - SN74LVC125ADR |
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