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CD74AC112M96 数据表(PDF) 4 Page - Texas Instruments |
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CD74AC112M96 数据表(HTML) 4 Page - Texas Instruments |
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4 / 11 page  CD54AC112, CD74AC112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS325 – JANUARY 2003 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements over recommended operating free-air temperature range, VCC = 1.5 V (unless otherwise noted) –55 °C to 125 °C –40 °C to 85 °C UNIT MIN MAX MIN MAX fclock Clock frequency 8 9 MHz t Pulse duration CLK high or low 63 55 ns tw Pulse duration CLR or PRE low 56 49 ns tsu Setup time, before CLK ↓ J or K 50 44 ns th Hold time, after CLK ↓ J or K 0 0 ns trec Recovery time, before CLK ↓ CLR ↑ or PRE↑ 31 27 ns timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) –55 °C to 125 °C –40 °C to 85 °C UNIT MIN MAX MIN MAX fclock Clock frequency 71 81 MHz t Pulse duration CLK high or low 7 6 ns tw Pulse duration CLR or PRE low 6.3 5.5 ns tsu Setup time, before CLK ↓ J or K 5.6 4.9 ns th Hold time, after CLK ↓ J or K 0 0 ns trec Recovery time, before CLK ↓ CLR ↑ or PRE↑ 3.5 3..1 ns timing requirements over recommended operating free-air temperature0 range, VCC = 5 V ± 0.5 V (unless otherwise noted) –55 °C to 125 °C –40 °C to 85 °C UNIT MIN MAX MIN MAX fclock Clock frequency 100 114 MHz t Pulse duration CLK high or low 5 4.4 ns tw Pulse duration CLR or PRE low 4.5 3.9 ns tsu Setup time, before CLK ↓ J or K 4 3.5 ns th Hold time, after CLK ↓ J or K 0 0 ns trec Recovery time, before CLK ↓ CLR ↑ or PRE↑ 2.5 2.2 ns |
类似零件编号 - CD74AC112M96 |
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类似说明 - CD74AC112M96 |
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