ZL50130 datasheet(36/60 Pages) ZARLINK

部件名	ZL50130

功能描述	Ethernet Pseudo-Wires across a PSN

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制造商	ZARLINK [Zarlink Semiconductor Inc]

网页	http://www.zarlink.com

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36 / 60 page

ZL50130

Data Sheet

36

Zarlink Semiconductor Inc.

4.4

System Function Interface

All System Function Interface signals are 5 V tolerant.

The core of the chip will be held in reset for 16383 SYSTEM_CLK cycles after SYSTEM_RST has gone HIGH to

allow the PLL’s to lock.

4.5

Test Facilities

4.5.1

Administration and Control Interface

All Administration and Control Interface signals are 5 V tolerant.

Signal

I/O

Package Balls

Description

SYSTEM_CLK

I

U6

System Clock Input. The system

clock frequency is 100 MHz. The

frequency must be accurate to

within ±32 ppm in synchronous

mode.

SYSTEM_RST

I

V4

System Reset Input. Active low.

The system reset is

asynchronous, and causes all

registers within the ZL50130 to

be reset to their default state.

SYSTEM_DEBUG

I

U5

System Debug Enable. This is

an asynchronous signal that,

when de-asserted, prevents the

software assertion of the

debug-freeze command,

regardless of the internal state

of registers, or any error

conditions. Active high.

Table 9 - System Function Interface Package Ball Definition

Signal

I/O

Package Balls

Description

GPIO[15:0]

ID/

OT

[15]

AA4

[7]

AA2

[14]

AB3

[6]

Y3

[13]

AC2

[5]

AB1

[12]

AC1

[4]

Y2

[11]

AB2

[3]

W4

[10]

Y4

[2]

V5

[9]

W5

[1]

AA1

[8]

AA3

[0]

W3

General Purpose I/O pins.

Connected to an internal

register, so customer can set

user-defined parameters. Bits

[4:0] reserved at startup or reset

for memory TDL setup. See the

ZL50130 Programmers Model

for more details.

TEST_MODE[2:0]

I D

[2]

AF6

[1]

AB9

[0]

AC8

Test Mode input - ensure these

pins are tied to ground for

normal operation.

000 SYS_NORMAL_MODE

001-010 RESERVED

011 SYS_TRISTATE_MODE

100-111 RESERVED

Table 10 - Administration/Control Interface Package Ball Definition

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