EP1C12F324I7ES datasheet(76/104 Pages) ALTERA

部件名	EP1C12F324I7ES

功能描述	Cyclone FPGA Family Data Sheet

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制造商	ALTERA [Altera Corporation]

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76 / 104 page

4–6

Altera Corporation

Preliminary

January 2007

Cyclone Device Handbook, Volume 1

Table 4–13. SSTL-3 Class I Specifications

Symbol

Parameter

Conditions

Minimum

Typical

Maximum

Unit

VCCIO

Output supply voltage

3.0

3.3

3.6

V

VTT

Termination voltage

VREF – 0.05

VREF

VREF + 0.05

V

VREF

Reference voltage

1.3

1.5

1.7

V

VIH

High-level input voltage

VREF + 0.2

VCCIO + 0.3

V

VIL

Low-level input voltage

–0.3

VREF – 0.2

V

VOH

High-level output voltage

IOH = –8 mA (11)

VTT + 0.6

V

VOL

Low-level output voltage

IOL = 8 mA (11)

VTT – 0.6

V

Table 4–14. SSTL-3 Class II Specifications

Symbol

Parameter

Conditions

Minimum

Typical

Maximum

Unit

VCCIO

Output supply voltage

3.0

3.3

3.6

V

VTT

Termination voltage

VREF – 0.05

VREF

VREF + 0.05

V

VREF

Reference voltage

1.3

1.5

1.7

V

VIH

High-level input voltage

VREF + 0.2

VCCIO + 0.3

V

VIL

Low-level input voltage

–0.3

VREF – 0.2

V

VOH

High-level output voltage

IOH = –16 mA

(11)

VTT + 0.8

V

VOL

Low-level output voltage

IOL = 16 mA (11)

VTT – 0.8

V

Table 4–15. Bus Hold Parameters

Parameter

Conditions

VCCIO Level

Unit

1.5 V1.8 V2.5 V3.3 V

Min

Max

Min

Max

Min

Max

Min

Max

Low sustaining

current

VIN > VIL

(maximum)

30

50

70

μA

High sustaining

current

VIN < VIH

(minimum)

–30

–50

–70

μA

Low overdrive

current

0 V < VIN <

VCCIO

200

300

500

μA

High overdrive

current

0 V < VIN <

VCCIO

–200

–300

–500

μA

类似零件编号 - EP1C12F324I7ES

制造商	部件名	数据表	功能描述
Altera Corporation	EP1C12F324I7	1Mb / 94P	Cyclone FPGA Family

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