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EP1C12F324C7ES 数据表(PDF) 9 Page - Altera Corporation |
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EP1C12F324C7ES 数据表(HTML) 9 Page - Altera Corporation |
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9 / 104 page  Altera Corporation 2–3 January 2007 Preliminary Logic Array Blocks Logic Array Blocks Each LAB consists of 10 LEs, LE carry chains, LAB control signals, a local interconnect, look-up table (LUT) chain, and register chain connection lines. The local interconnect transfers signals between LEs in the same LAB. LUT chain connections transfer the output of one LE's LUT to the adjacent LE for fast sequential LUT connections within the same LAB. Register chain connections transfer the output of one LE's register to the adjacent LE's register within an LAB. The Quartus® II Compiler places associated logic within an LAB or adjacent LABs, allowing the use of local, LUT chain, and register chain connections for performance and area efficiency. Figure 2–2 details the Cyclone LAB. Figure 2–2. Cyclone LAB Structure LAB Interconnects The LAB local interconnect can drive LEs within the same LAB. The LAB local interconnect is driven by column and row interconnects and LE outputs within the same LAB. Neighboring LABs, PLLs, and M4K RAM blocks from the left and right can also drive an LAB's local interconnect through the direct link connection. The direct link connection feature minimizes the use of row and column interconnects, providing higher Direct link interconnect from adjacent block Direct link interconnect to adjacent block Row Interconnect Column Interconnect Local Interconnect LAB Direct link interconnect from adjacent block Direct link interconnect to adjacent block |
类似零件编号 - EP1C12F324C7ES |
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类似说明 - EP1C12F324C7ES |
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