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EP1C20F400C7ES 数据表(PDF) 80 Page - Altera Corporation |
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EP1C20F400C7ES 数据表(HTML) 80 Page - Altera Corporation |
80 / 104 page 4–10 Altera Corporation Preliminary January 2007 Cyclone Device Handbook, Volume 1 Performance The maximum internal logic array clock tree frequency is limited to the specifications shown in Table 4–19. Table 4–20 shows the Cyclone device performance for some common designs. All performance values were obtained with the Quartus II software compilation of library of parameterized modules (LPM) functions or megafunctions. These performance values are based on EP1C6 devices in 144-pin TQFP packages. Table 4–19. Clock Tree Maximum Performance Specification Parameter Definition -6 Speed Grade -7 Speed Grade -8 Speed Grade Units Min Typ Max Min Typ Max Min Typ Max Clock tree fMAX Maximum frequency that the clock tree can support for clocking registered logic 405 320 275 MHz Table 4–20. Cyclone Device Performance Resource Used Design Size & Function Mode Resources Used Performance LEs M4K Memory Bits M4K Memory Blocks -6 Speed Grade (MHz) -7 Speed Grade (MHz) -8 Speed Grade (MHz) LE 16-to-1 multiplexer - 21 - - 405.00 320.00 275.00 32-to-1 multiplexer - 44 - - 317.36 284.98 260.15 16-bit counter - 16 - - 405.00 320.00 275.00 64-bit counter (1) - 66 - - 208.99 181.98 160.75 |
类似零件编号 - EP1C20F400C7ES |
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类似说明 - EP1C20F400C7ES |
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