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EP1C12F324I6ES 数据表(PDF) 86 Page - Altera Corporation |
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EP1C12F324I6ES 数据表(HTML) 86 Page - Altera Corporation |
86 / 104 page 4–16 Altera Corporation Preliminary January 2007 Cyclone Device Handbook, Volume 1 Figure 4–2. External Timing in Cyclone Devices All external I/O timing parameters shown are for 3.3-V LVTTL I/O standard with the maximum current strength and fast slew rate. For external I/O timing using standards other than LVTTL or for different current strengths, use the I/O standard input and output delay adders in Tables 4–40 through 4–44. Table 4–29 shows the external I/O timing parameters when using global clock networks. PRN CLRN DQ PRN CLRN DQ PRN CLRN DQ Dedicated Clock Bidirectional Pin Output Register Input Register OE Register tXZ tZX tINSU tINH tOUTCO Table 4–29. Cyclone Global Clock External I/O Timing Parameters Notes (1), (2) (Part 1 of 2) Symbol Parameter Conditions tINSU Setup time for input or bidirectional pin using IOE input register with global clock fed by CLK pin tINH Hold time for input or bidirectional pin using IOE input register with global clock fed by CLK pin tOUTCO Clock-to-output delay output or bidirectional pin using IOE output register with global clock fed by CLK pin CLOAD = 10 pF tINSUPLL Setup time for input or bidirectional pin using IOE input register with global clock fed by Enhanced PLL with default phase setting tINHPLL Hold time for input or bidirectional pin using IOE input register with global clock fed by enhanced PLL with default phase setting |
类似零件编号 - EP1C12F324I6ES |
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类似说明 - EP1C12F324I6ES |
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