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EP1C6F256I6ES 数据表(PDF) 81 Page - Altera Corporation |
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EP1C6F256I6ES 数据表(HTML) 81 Page - Altera Corporation |
81 / 104 page Altera Corporation 4–11 January 2007 Preliminary Timing Model Internal Timing Parameters Internal timing parameters are specified on a speed grade basis independent of device density. Tables 4–21 through 4–24 describe the Cyclone device internal timing microparameters for LEs, IOEs, M4K memory structures, and MultiTrack interconnects. M4K memory block RAM 128 × 36 bit Single port - 4,608 1 256.00 222.67 197.01 RAM 128 × 36 bit Simple dual-port mode - 4,608 1 255.95 222.67 196.97 RAM 256 × 18 bit True dual- port mode - 4,608 1 255.95 222.67 196.97 FIFO 128 × 36 bit - 40 4,608 1 256.02 222.67 197.01 Shift register 9×4×128 Shift register 11 4,536 1 255.95 222.67 196.97 Note to Table 4–20: (1) The performance numbers for this function are from an EP1C6 device in a 240-pin PQFP package. Table 4–20. Cyclone Device Performance Resource Used Design Size & Function Mode Resources Used Performance LEs M4K Memory Bits M4K Memory Blocks -6 Speed Grade (MHz) -7 Speed Grade (MHz) -8 Speed Grade (MHz) Table 4–21. LE Internal Timing Microparameter Descriptions Symbol Parameter tSU LE register setup time before clock tH LE register hold time after clock tCO LE register clock-to-output delay tLUT LE combinatorial LUT delay for data-in to data-out tCLR Minimum clear pulse width tPRE Minimum preset pulse width tCLKHL Minimum clock high or low time |
类似零件编号 - EP1C6F256I6ES |
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类似说明 - EP1C6F256I6ES |
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