EP1C12F324C6ES datasheet(97/104 Pages) ALTERA

部件名	EP1C12F324C6ES

功能描述	Cyclone FPGA Family Data Sheet

Download	104 Pages

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制造商	ALTERA [Altera Corporation]

网页	http://www.altera.com

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97 / 104 page

Altera Corporation

4–27

January 2007

Preliminary

Timing Model

Maximum Input & Output Clock Rates

Tables 4–48 and 4–49 show the maximum input clock rate for column and

row pins in Cyclone devices.

Table 4–47. Cyclone IOE Programmable Delays on Row Pins

Parameter

Setting

-6 Speed Grade

-7 Speed Grade

-8 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

Decrease input delay to

internal cells

Off

154

177

200

ps

Small

2,212

2,543

2,875

ps

Medium

2,639

3,034

3,430

ps

Large

3,057

3,515

3,974

ps

On

154

177

200

ps

Decrease input delay to input

register

Off

000

ps

On

3,057

3,515

3,974

ps

Increase delay to output pin

Off

0

ps

On

556

639

722

ps

Note to Table 4–47:

(1)

EPC1C3 devices do not support the PCI I/O standard

Table 4–48. Cyclone Maximum Input Clock Rate for Column Pins

I/O Standard

-6 Speed

Grade

-7 Speed

Grade

-8 Speed

Grade

Unit

LVTTL

464

428

387

MHz

2.5 V

392

302

207

MHz

1.8 V

387

311

252

MHz

1.5 V

387

320

243

MHz

LVCMOS

405

374

333

MHz

SSTL-3 class I

405

356

293

MHz

SSTL-3 class II

414

365

302

MHz

SSTL-2 class I

464

428

396

MHz

SSTL-2 class II

473

432

396

MHz

LVDS

567

549

531

MHz

类似零件编号 - EP1C12F324C6ES

制造商	部件名	数据表	功能描述
Altera Corporation	EP1C12F324C6	1Mb / 94P	Cyclone FPGA Family

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