EP1C3T144C6ES datasheet(92/104 Pages) ALTERA

部件名	EP1C3T144C6ES

功能描述	Cyclone FPGA Family Data Sheet

Download	104 Pages

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制造商	ALTERA [Altera Corporation]

网页	http://www.altera.com

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92 / 104 page

4–22

Altera Corporation

Preliminary

January 2007

Cyclone Device Handbook, Volume 1

SSTL-2 class II

−278

−320

−362

ps

LVDS

−261

−301

−340

ps

Table 4–41. Cyclone I/O Standard Row Pin Input Delay Adders

I/O Standard

-6 Speed Grade

-7 Speed Grade

-8 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

LVCMOS

000

ps

3.3-V LVTTL

0

ps

2.5-V LVTTL

27

31

35

ps

1.8-V LVTTL

182

209

236

ps

1.5-V LVTTL

278

319

361

ps

3.3-V PCI (1)

000

ps

SSTL-3 class I

−250

−288

−325

ps

SSTL-3 class II

−250

−288

−325

ps

SSTL-2 class I

−278

−320

−362

ps

SSTL-2 class II

−278

−320

−362

ps

LVDS

−261

−301

−340

ps

Table 4–42. Cyclone I/O Standard Output Delay Adders for Fast Slew Rate on Column Pins (Part 1 of 2)

Standard

-6 Speed Grade

-7 Speed Grade

-8 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

LVCMOS

2 mA

0

ps

4 mA

−489

−563

−636

ps

8 mA

−855

−984

−1,112

ps

12 mA

−993

−1,142

−1,291

ps

3.3-V LVTTL

4 mA

0

ps

8 mA

−347

−400

−452

ps

12 mA

−858

−987

−1,116

ps

16 mA

−819

−942

−1,065

ps

24 mA

−993

−1,142

−1,291

ps

Table 4–40. Cyclone I/O Standard Column Pin Input Delay Adders (Part 2 of 2)

I/O Standard

-6 Speed Grade

-7 Speed Grade

-8 Speed Grade

Unit

Min

Max

Min

Max

Min

Max

类似零件编号 - EP1C3T144C6ES

制造商	部件名	数据表	功能描述
Altera Corporation	EP1C3T144C6	1Mb / 94P	Cyclone FPGA Family

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