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EP1C3T144C6ES 数据表(PDF) 64 Page - Altera Corporation |
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EP1C3T144C6ES 数据表(HTML) 64 Page - Altera Corporation |
64 / 104 page 3–2 Altera Corporation Preliminary January 2007 Cyclone Device Handbook, Volume 1 In the Quartus II software, there is an Auto Usercode feature where you can choose to use the checksum value of a programming file as the JTAG user code. If selected, the checksum is automatically loaded to the USERCODE register. Choose Assignments > Device > Device and Pin Options > General. Turn on Auto Usercode. USERCODE 00 0000 0111 Selects the 32-bit USERCODE register and places it between the TDI and TDO pins, allowing the USERCODE to be serially shifted out of TDO. IDCODE 00 0000 0110 Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE to be serially shifted out of TDO. HIGHZ (1) 00 0000 1011 Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation, while tri-stating all of the I/O pins. CLAMP (1) 00 0000 1010 Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation while holding I/O pins to a state defined by the data in the boundary-scan register. ICR instructions Used when configuring a Cyclone device via the JTAG port with a MasterBlasterTM or ByteBlasterMVTM download cable, or when using a Jam File or Jam Byte-Code File via an embedded processor. PULSE_NCONFIG 00 0000 0001 Emulates pulsing the nCONFIG pin low to trigger reconfiguration even though the physical pin is unaffected. CONFIG_IO 00 0000 1101 Allows configuration of I/O standards through the JTAG chain for JTAG testing. Can be executed before, after, or during configuration. Stops configuration if executed during configuration. Once issued, the CONFIG_IO instruction will hold nSTATUS low to reset the configuration device. nSTATUS is held low until the device is reconfigured. SignalTap II instructions Monitors internal device operation with the SignalTap II embedded logic analyzer. Note to Table 3–1: (1) Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST. Table 3–1. Cyclone JTAG Instructions (Part 2 of 2) JTAG Instruction Instruction Code Description |
类似零件编号 - EP1C3T144C6ES |
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类似说明 - EP1C3T144C6ES |
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