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EP1C20F400C6ES 数据表(PDF) 46 Page - Altera Corporation

部件名 EP1C20F400C6ES
功能描述  Cyclone FPGA Family Data Sheet
Download  104 Pages
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation

EP1C20F400C6ES 数据表(HTML) 46 Page - Altera Corporation

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Altera Corporation
Preliminary
January 2007
Cyclone Device Handbook, Volume 1
Figure 2–27. Cyclone IOE Structure
Note to Figure 2–27:
(1)
There are two paths available for combinatorial inputs to the logic array. Each path
contains a unique programmable delay chain.
The IOEs are located in I/O blocks around the periphery of the Cyclone
device. There are up to three IOEs per row I/O block and up to three IOEs
per column I/O block (column I/O blocks span two columns). The row
I/O blocks drive row, column, or direct link interconnects. The column
I/O blocks drive column interconnects. Figure 2–28 shows how a row
I/O block connects to the logic array. Figure 2–29 shows how a column
I/O block connects to the logic array.
Output Register
Output
Combinatorial
input (1)
Input
OE Register
OE
Input Register
Logic Array
DQ
DQ
DQ


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