SN54LV00, SN74LV00

QUADRUPLE 2-INPUT POSITIVE-NAND GATES

SCLS182C – FEBRUARY 1993 – REVISED APRIL 1996

1

POST OFFICE BOX 655303

CMOS) 2-

µ Process

MIL-STD-883C, Method 3015; Exceeds

200 V Using Machine Model

(C = 200 pF, R = 0)

Per JEDEC Standard JESD-17

Small-Outline (D), Shrink Small-Outline

(DB), Thin Shrink Small-Outline (PW),

Ceramic Flat (W) Packages, Chip Carriers

(FK), and (J) 300-mil DIPs

description

These quadruple 2-input positive-NAND gates

The

’LV00

perform

the

Boolean

function

Y = A

• B or Y = A + B in positive logic.

The SN74LV00 is available in TI’s shrink

small-outline package (DB), which provides the

same I/O pin count and functionality of standard

small-outline packages in less than half the

printed-circuit-board area.

The SN54LV00 is characterized for operation over the full military temperature range of –55

°C to 125°C. The

SN74LV00 is characterized for operation from –40

°C to 85°C.

FUNCTION TABLE

(each gate)

INPUTS

OUTPUT

A

B

Y

H

H

L

L

XH

X

L

H

Copyright

© 1996, Texas Instruments Incorporated

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

SN54LV00 ...J OR W PACKAGE

SN74LV00 . . . D, DB, OR PW PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1A

1B

1Y

2A

2B

2Y

GND

4B

4A

4Y

3B

3A

3Y

32

1 20 19

910 11 12 13

4

5

6

7

8

18

17

16

15

14

4A

NC

4Y

NC

3B

1Y

NC

2A

NC

2B

SN54LV00 . . . FK PACKAGE

(TOP VIEW)

NC – No internal connection

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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.