ADP1653ACPZ-R71 datasheet(5/24 Pages) AD

部件名	ADP1653ACPZ-R71

功能描述	Compact, High Efficiency, High Power Flash/Torch LED Driver with Dual Interface

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制造商	AD [Analog Devices]

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ADP1653

Rev. A | Page 5 of 24

I2C TIMING SPECIFICATIONS

Table 2.

Parameter

Min

Max

Unit

Description

fSCL

400

kHz

SCL clock frequency

tHIGH

0.6

μs

SCL high time

tLOW

1.3

μs

SCL low time

tSU, DAT

100

ns

Data setup time

tHD, DAT1

0

0.9

μs

Data hold time

tSU, STA

0.6

μs

Setup time for repeated start

tHD, STA

0.6

μs

Hold time for start/repeated start

tBUF

1.3

μs

Bus free time between a stop and a start condition

tSU, STO

0.6

μs

Setup time for stop condition

tR

20 + 0.1 CB

300

ns

Rise time of SCL and SDA

tF

20 + 0.1 CB

300

ns

Fall time of SCL and SDA

tSP

0

50

ns

Pulse width of suppressed spike

CB2

400

pF

Capacitive load for each bus line

1 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH minimum of the SCL signal) to bridge the undefined region of the

SCL falling edge.

2 CB is the total capacitance of one bus line in picofarads.

SDA

SCL

S

S = START CONDITION

Sr = REPEATED START CONDITION

P = STOP CONDITION

Sr

P

S

tLOW

tR

tHD, DAT

tHIGH

tSU, DAT

tF

tSU, STA

tHD, STA

tSP

tSU, STO

tBUF

tR

Figure 3. I2C Interface Timing Diagram

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