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APEX20K Datasheet(数据表) 3 Page - Altera Corporation

部件型号  APEX20K
说明  Programmable Logic Device Family
下载  117 Pages
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation

APEX20K Datasheet(HTML) 3 Page - Altera Corporation

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Altera Corporation
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APEX 20K Programmable Logic Device Family Data Sheet
Flexible clock management circuitry with up to four phase-locked
loops (PLLs)
Built-in low-skew clock tree
Up to eight global clock signals
ClockLock® feature reducing clock delay and skew
ClockBoost® feature providing clock multiplication and division
ClockShiftTM programmable clock phase and delay shifting
Powerful I/O features
Compliant with peripheral component interconnect Special
Interest Group (PCI SIG) PCI Local Bus Specification,
Revision 2.2
for 3.3-V operation at 33 or 66 MHz and 32 or 64 bits
Support for high-speed external memories, including DDR
SDRAM and ZBT SRAM (ZBT is a trademark of Integrated
Device Technology, Inc.)
Bidirectional I/O performance (tCO + tSU) up to 250 MHz
LVDS performance up to 840 Mbits per channel
Direct connection from I/O pins to local interconnect providing
fast tCO and tSU times for complex logic
MultiVolt I/O interface support to interface with 1.8-V, 2.5-V,
3.3-V, and 5.0-V devices (see Table 3)
Programmable clamp to VCCIO
Individual tri-state output enable control for each pin
Programmable output slew-rate control to reduce switching
noise
Support for advanced I/O standards, including low-voltage
differential signaling (LVDS), LVPECL, PCI-X, AGP, CTT, stub-
series terminated logic (SSTL-3 and SSTL-2), Gunning
transceiver logic plus (GTL+), and high-speed terminated logic
(HSTL Class I)
Pull-up on I/O pins before and during configuration
Advanced interconnect structure
Four-level hierarchical FastTrack® Interconnect structure
providing fast, predictable interconnect delays
Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
Dedicated cascade chain that implements high-speed,
high-fan-in logic functions (automatically used by software tools
and megafunctions)
Interleaved local interconnect allows one LE to drive 29 other
LEs through the fast local interconnect
Advanced packaging options
Available in a variety of packages with 144 to 1,020 pins (see
Tables 4 through 7)
FineLine BGA® packages maximize board space efficiency
Advanced software support
Software design support and automatic place-and-route
provided by the Altera® Quartus® II development system for




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