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APEX20K 数据表(PDF) 73 Page - Altera Corporation |
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APEX20K 数据表(HTML) 73 Page - Altera Corporation |
73 / 117 page Altera Corporation 73 APEX 20K Programmable Logic Device Family Data Sheet Tables 32 and 33 describe APEX 20K external timing parameters. tESBDATACO2 ESB clock-to-output delay without output registers tESBDD ESB data-in to data-out delay for RAM mode tPD ESB macrocell input to non-registered output tPTERMSU ESB macrocell register setup time before clock tPTERMCO ESB macrocell register clock-to-output delay tF1-4 Fanout delay using local interconnect tF5-20 Fanout delay using MegaLab Interconnect tF20+ Fanout delay using FastTrack Interconnect tCH Minimum clock high time from clock pin tCL Minimum clock low time from clock pin tCLRP LE clear pulse width tPREP LE preset pulse width tESBCH Clock high time tESBCL Clock low time tESBWP Write pulse width tESBRP Read pulse width Table 31. APEX 20K fMAX Timing Parameters (Part 2 of 2) Symbol Parameter Table 32. APEX 20K External Timing Parameters Note (1) Symbol Clock Parameter tINSU Setup time with global clock at IOE register tINH Hold time with global clock at IOE register tOUTCO Clock-to-output delay with global clock at IOE register Table 33. APEX 20K External Bidirectional Timing Parameters Note (1) Symbol Parameter Conditions tINSUBIDIR Setup time for bidirectional pins with global clock at same-row or same- column LE register tINHBIDIR Hold time for bidirectional pins with global clock at same-row or same- column LE register tOUTCOBIDIR Clock-to-output delay for bidirectional pins with global clock at IOE register C1 = 10 pF tXZBIDIR Synchronous IOE output buffer disable delay C1 = 10 pF tZXBIDIR Synchronous IOE output buffer enable delay, slow slew rate = off C1 = 10 pF |
类似零件编号 - APEX20K |
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类似说明 - APEX20K |
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