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CAT140081SWI-GT3 数据表(PDF) 8 Page - Catalyst Semiconductor

部件名 CAT140081SWI-GT3
功能描述  Voltage Supervisor with I2C Serial CMOS EEPROM
Download  14 Pages
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制造商  CATALYST [Catalyst Semiconductor]
网页  http://www.catalyst-semiconductor.com
标志 CATALYST - Catalyst Semiconductor

CAT140081SWI-GT3 数据表(HTML) 8 Page - Catalyst Semiconductor

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CAT140xx
Doc. No. 1117 Rev. A
8
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
WRITE OPERATIONS
Byte Write
In Byte Write mode, the Master sends the START
condition and the Slave address with the R/W bit set
to zero to the Slave. After the Slave generates an
acknowledge, the Master sends the byte address that
is to be written into the address pointer of the
CAT140xx. After receiving another acknowledge from
the Slave, the Master transmits the data byte to be
written into the addressed memory location. The
CAT140xx device will acknowledge the data byte and
the Master generates the STOP condition, at which
time the device begins its internal Write cycle to
nonvolatile memory (Figure 7). While this internal
cycle is in progress (tWR), the SDA output will be tri-
stated and the CAT140xx will not respond to any
request from the Master device (Figure 8).
Page Write
The CAT140xx writes up to 16 bytes of data in a
single write cycle, using the Page Write operation
(Figure 9). The Page Write operation is initiated in the
same manner as the Byte Write operation, however
instead of terminating after the data byte is
transmitted, the Master is allowed to send up to fifteen
additional bytes. After each byte has been transmitted
the CAT140xx will respond with an acknowledge and
internally increments the four low order address bits.
The high order bits that define the page address
remain unchanged. If the Master transmits more than
sixteen bytes prior to sending the STOP condition, the
address counter ‘wraps around’ to the beginning of
page and previously transmitted data will be
overwritten. Once all sixteen bytes are received and
the STOP condition has been sent by the Master, the
internal Write cycle begins. At this point all received
data is written to the CAT140xx in a single write cycle.
Acknowledge Polling
The acknowledge (ACK) polling routine can be used
to take advantage of the typical write cycle time.
Once the stop condition is issued to indicate the end
of the host’s write operation, the CAT140xx initiates
the internal write cycle.
The ACK polling can be
initiated immediately. This involves issuing the start
condition followed by the slave address for a write
operation. If the CAT140xx is still busy with the write
operation, NoACK will be returned. If the CAT140xx
has completed the internal write operation, an ACK
will be returned and the host can then proceed with
the next read or write operation.


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