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HY5PS1G1631CFP-C4 数据表(PDF) 18 Page - Hynix Semiconductor |
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HY5PS1G1631CFP-C4 数据表(HTML) 18 Page - Hynix Semiconductor |
18 / 37 page Rev. 0.2 /Dec 2006 18 HY5PS1G431C(L)FP HY5PS1G831C(L)FP HY5PS1G1631C(L)FP Note : 1. VDDQ = 1.8 +/- 0.1V ; VDD = 1.8 +/- 0.1V (exclusively VDDQ = 1.9 +/- 0.1V ; VDD = 1.9 +/- 0.1V for C3 speed grade) 2. IDD specifications are tested after the device is properly initialized 3. Input slew rate is specified by AC Parametric Test Condition 4. IDD parameters are specified with ODT disabled. 5. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combinations of EMRS bits 10 and 11. 6. Definitions for IDD LOW is defined as Vin £ VILAC(max) HIGH is defined as Vin Š VIHAC(min) STABLE is defined as inputs stable at a HIGH or LOW level FLOATING is defined as inputs at VREF = VDDQ/2 SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes. |
类似零件编号 - HY5PS1G1631CFP-C4 |
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类似说明 - HY5PS1G1631CFP-C4 |
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