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ADM1487EARZ 数据表(PDF) 4 Page - Analog Devices

部件名 ADM1487EARZ
功能描述  5 V, 짹15 kV ESD Protected Half-Duplex, RS-485/RS-422 Transceivers
Download  16 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADM1487EARZ 数据表(HTML) 4 Page - Analog Devices

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ADM485E/ADM487E/ADM1487E
Rev. 0 | Page 4 of 16
TIMING SPECIFICATIONS
VCC = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted.
Table 3. ADM485E/ADM1487E
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
DRIVER
Input to Output
tDPLH
10
40
60
ns
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
tDPHL
10
40
60
ns
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
Output Skew to Output
tSKEW
5
10
ns
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
Rise/Fall Time
tDR, tDF
3
20
40
ns
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
Enable Time to High Level
tDZH
45
70
ns
CRL = 100 pF, S2 closed (see Figure 21)
Enable Time to Low Level
tDZL
45
70
ns
CRL = 100 pF, S1 closed (see Figure 22)
Disable Time from Low Level
tDLZ
45
70
ns
CRL = 15 pF, S1 closed (see Figure 22)
Disable Time from High Level
tDHZ
45
70
ns
CRL = 15 pF, S2 closed (see Figure 21)
RECEIVER
Input to Output
tRPLH
20
60
200
ns
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 23 and Figure 24)
|tPLH − tPHL| Differential Receiver Skew
tSKEW
5
ns
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 4 and Figure 5)
Enable Time to Low Level
tRZL
25
50
ns
CRL = 15 pF, S2 closed (see Figure 25)
Enable Time to High Level
tRZL
20
50
ns
CRL = 15 pF, S1 closed (see Figure 25)
Disable Time from Low Level
tRLZ
20
50
ns
CRL = 15 pF, S2 closed (see Figure 25)
Disable Time from High Level
tRHZ
20
50
ns
tPLH, tPHL < 50% of data period
MAXIMUM DATA RATE
fMAX
2.5
Mbps


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