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HY5PS1G821LM 数据表(PDF) 27 Page - Hynix Semiconductor |
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HY5PS1G821LM 数据表(HTML) 27 Page - Hynix Semiconductor |
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27 / 79 page  Rev. 0.2 / Oct. 2005 27 1HY5PS12421(L)M HY5PS12821(L)M 2.5.1 Posted CAS Posted CAS operation is supported to make command and data bus efficient for sustainable bandwidths in DDR2 SDRAM. In this operation, the DDR2 SDRAM allows a CAS read or write command to be issued immediately after the RAS bank activate command (or any time during the RAS-CAS-delay time, tRCD, period). The command is held for the time of the Additive Latency (AL) before it is issued inside the device. The Read Latency (RL) is controlled by the sum of AL and the CAS latency (CL). Therefore if a user chooses to issue a R/W command before the tRCDmin, then AL (greater than 0) must be written into the EMRS(1). The Write Latency (WL) is always defined as RL - 1 (read latency -1) where read latency is defined as the sum of additive latency plus CAS latency (RL=AL+CL). Read or Write operations using AL allow seamless bursts (refer to semaless operation timing diagram examples in Read burst and Wirte burst section) Examples of posted CAS operation Example 1 Read followed by a write to the same bank [AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL - 1) = 4, BL = 4] Example 2 Read followed by a write to the same bank [AL = 0 and CL = 3, RL = (AL + CL) = 3, WL = (RL - 1) = 2, BL = 4] 0 1 2 3 45 67 8 9 10 11 12 Active A-Bank Read A-Bank Write A-Bank Dout0 Dout1 Dout2 Dout3 Din0 Din1 Din2 Din3 CK/CK CMD DQS/DQS DQ AL = 2 -1 > = tRCD CL = 3 > = tRAC WL = RL -1 = 4 RL = AL + CL = 5 Active A-Bank Read A-Bank Write A-Bank Dout0 Dout1 Dout2 Dout3 Din0 Din1 Din2 Din3 AL = 0 > = tRCD CL = 3 > = tRAC WL = RL -1 = 2 RL = AL + CL = 3 0 1 2 3 4 5 6 7 8 9 10 11 12 -1 CK/CK CMD DQS/DQS DQ |
类似零件编号 - HY5PS1G821LM |
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类似说明 - HY5PS1G821LM |
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